Chun-Deok Suh

A fast frequency/mode switching quadrature SSB mixer/amplifier for the low power MTG in MB-OFDM UWB radio transceiver

A fast frequency/mode switching SSB mixer/amplifier topology is proposed for the implementation of low power multi-tone generator (MTG) in MB-OFDM UWB system. The proposed SSB mixer/amplifier topology is fabricated for the generation of mode-1 band center carrier with 0.18mum CMOS technology. The measurement result shows the 8.5ns mixer/amplifier mode switching time. The center carrier output power levels are -13.0dBm, -12.88dBm, and -14.33dBm in 3432MHz, 3960MHz, and 4488MHz, respectively. The harmonic suppressions are -40dBc and -30dBc in 3432MHz and 4488MHz, where the SSB mixer mode is selected. In the amplifier mode, the 3960MHz tone does not have any harmonics tone. For measurement, 1.8V supply voltage is used while drawing 26mA total current

A 3–10 GHz flexible CMOS LO generator for MB-OFDM UWB application using wide tunable VCOs

A frequency synthesizer for MB-OFDM UWB system is implemented in CMOS RF process. The LO generator includes three wide tunable VCOs, PLLs, and quadrature generators. This synthesizer with three VCOs gives more flexible power management scheme and generates lower spurious tones than single side-band mixing method. This scheme supports all band groups except band group 2 which wireless LAN application occupies. Local oscillator including PLLs consumes 17.8 ~ 45.7 mA according to TFC code from 1.2 V power supply. Phase noise has been measured less than -100 dBc/Hz over the operating frequency range.

A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology

We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog ICs.

A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology

A 3 to 5 GHz fast hopping frequency synthesizer for multi-band OFDM UWB applications is designed using a 0.18 mum CMOS technology. The frequency synthesizer operates in the mode 1 bands (centered at 3432 MHz, 3960 MHz, and 4488 MHz). Single-sideband mixer up-converts or down-converts the 528 MHz quadrature signals of ring VCO mixing 3960 MHz LC VCO signals. The sideband suppression is less than -32 dBc for 3432 MHz and -26 dBc for 4488 MHz and band switching time from 4488 MHz to 3432 MHz is measured about 2 ns. Phase noise of the LC VCO and the ring VCO is about -110 dBc/Hz and -98 dBc/Hz at 1 MHz offset frequency, respectively. The total power consumption of the proposed frequency synthesizer is about 68 mW with a 1.8 V supply voltage

Analog Baseband Chain in a 0.18 μm Standard Digital CMOS Technology for IEEE802.15.3a (UWB) Receiver

Today UWB (ultra-wideband) communication is gaining a great attention from consumer electronic-industry and is expected to be adopted for many WPAN (wireless personal area network) applications. UWB (Ultra- wideband) communication standard is based the form of direct sequence or OFDM (orthogonal frequency division multiplexing) for high-date-rate application like IEEE 802.15.3a [1]. This paper demonstrates a successful implementation and experimental verification of a CMOS analog baseband chain - variable gain amplifier and low pass filter - for a UWB wireless PAN (personal area network) receiver in a 0.18 μm CMOS process. The experiments features 40 dB linear scaled output gain and a total current of 30 mA.