ongyeun Cho

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

A complementary LC-VCO is integrated in a 65nm SOI process and is statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz and frequency tuning range is 6.14GHz or 9.05%. It achieves a phase noise of -106dBc/Hz at 10MHz offset and consumes 5.37mW from a 1.2V supply. The VCO yield is 94.7% for 70GHz operation.

CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement

A mixed-signal circuits performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process variations. A current-controlled oscillators performance and device threshold voltages are cross-correlated using simulation and RF measurement. Up to 93.9% cross-correlation between oscillation frequency and device threshold voltage is obtained, and strong model-to-hardware correlation is observed through statistical analysis of simulation result and circuit measurement. The yield learning process of design, simulation, measurement, and statistical analysis is proposed

SOI CMOS Technology with 360GHz f T NFET, 260GHz f T PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog System-on-Chip Applications

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fTs of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipating 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.

A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS

As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels. This has also served as a standard benchmark vehicle that reveals high-speed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled, and they are comparable to dividers in other technologies. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the fdiv , max, the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to injection-locking dividers. When the circuit sensitivity curve is measured, it is not clear where to set the threshold. Depending on the method, a sensitivity curve can be optimistic or pessimistic. A similar problem lies in the fdiv , max, since it changes depending on the status of a divider. Also, there have not been any analytic results that can interpret the circuit parameters and performance, in spite of the common use of sensitivity curve in literatures.

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configurations pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.

Wideband mmWave CML static divider in 65nm SOI CMOS technology

A wideband millimeter-wave (mmWave) CML static divider fabricated in 65 nm SOI CMOS technology is presented. The mmWave system realization trend and engagement in sub-100 nm CMOS technologies are summarized. CML static dividerpsilas circuit analysis, sensitivity curve, and simulations are explored. The input-locking hysteresis and divider DC bias tuning are employed to extend the divider operation range. The divider performance measurements are presented with hysteresis-assisted gain and figure-of-merits. A scalable statistical estimation is proposed, and it is validated with a full 300 mm wafer measurements. The divider exhibits wideband mmWave performance to overcome the process variability in sub-100 nm CMOS processes.

An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS

CMOS VCOs have been implemented for mm-wave applications [1–7], however, as the required channel bandwidth for these applications increases, wide-range VCO tuning is becoming more challenging. Even without taking into account the process variability in nanometer CMOS, a single VCO hardly achieves requirements for a mm-wave band and phase-noise performance, and it suffers from the steep VCO loop gain. Taking advantage of parallelism, using an array of VCOs is emerging as an alternative technique to implement a wide-band VCO (Fig. 16.3.1). While nanometer CMOS technology is becoming the next generation RF and mm-wave platform (because of high-speed performance due to technology scaling and and SoC integration capability), costly technology developments and mask sets further promote the use of array-based VCOs to expedite yield learning and circuit-development cycle. However, a VCO array requires more circuit area. Conventional designs are not scalable because of their size, cost, and complications for signal delivery. Technology scaling for mm-wave SoC is driven by the high-speed device performance while digital systems benefit from increased device density. In mm-wave applications, passive components, especially inductors, are responsible for area budget, since their area is not scaled with the technology. Taking advantage of nanometer FETs, the presented complementary LC-VCO is attractive for VCO arrays. It uses an LC-tank and its area is minimal and highly scalable. The use of state-of-the-art nanometer CMOS technology is essential to retain high-speed design margin for mm-wave circuits and provisions are required to make the complementary LC-VCO more scalable and manufacturable against the process variability and technology uncertainty. After all, the VCO array provides mm-wave-component performance-variability metrics as a feedback to the technology foundry. Such components are difficult and expensive to characterize and the required on-chip probe pads waste silicon area.

Statistical framework for technology-model-product co-design and convergence

This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data- driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates systematic process variations on die-to-die and wafer-to-wafer levels is also presented. The proposed framework enables translations of interactions among technology, product, and model, and facilitates collaborative efforts accordingly. The proposed methodology has been applied to first three development generations of 65 nm technology node and microprocessor product current-controlled oscillators (ICOs) for phase-locked loops (PLLs) that were migrated from 90 nm. Automated manufacturing floor in-line characterization and bench RF measurements are used for the methodology. The ICO exhibits yield improvement of RF oscillation frequency from 47% to 99% across three different 65 nm SOI technology generations.

Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.