Mahender Kumar

A LDMOS technology compatible with CMOS and passive components for integrated RF power amplifiers

The authors describe a bulk silicon LDMOS technology, which is compatible with CMOS and passive components, for the implementation of RF integrated power amplifiers (IPAs) used in portable wireless communication applications. This technology allows complete integration of the low cost and low power front-end circuits with the baseband circuits for single-chip wireless communication systems. The LDMOS transistor (0.35 /spl mu/m channel length, 3.85 /spl mu/m drift length, 3 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length), and high Q-factor (up to 6.10 at 900 MHz and 7.14 at 1.8 GHz) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation.

A 900 MHz SOI fully-integrated RF power amplifier for wireless transceivers

This 900 MHz fully-integrated power amplifier (IPA) for the first time uses SOI lateral double-diffused MOS transistors (LDMOSTs) and high-Q on-chip inductors. The IPA uses a 1.5 /spl mu/m LDMOS (0.35 /spl mu/m channel length 3.85 /spl mu/m drift length 4.5 GHz f/sub T/, 20 V breakdown) technology, which is compatible with CMOS and BJT for baseband and receiver functions. This makes it suitable for single-chip transceiver application. The IPA delivers +23 dBm output power with 16 dB gain and 49% power added efficiency (PAE) at 900 MHz, and is suitable for mobile phone handset application.

A simple, high performance TFSOI complementary BiCMOS technology for low power wireless applications

The authors describe a simple, high performance thin-film silicon-on-insulator (TFSOI) complementary BiCMOS (C-BiCMOS) technology, which can be used in low power wireless communication applications. In this technology, a novel, high performance lateral BJT structure is implemented using a gate spacer to obtain a thin base width and a minimum base linkage to the external base for minimized base resistance. A lateral NPN transistor (with maximum oscillation frequency (f/sub max/) of 29 GHz, cut-off frequency (f/sub T/) of 8 GHz, current gain (h/sub FE/) of 78, and collect-emitter breakdown voltage with base open (BV/sub CEO/) of 5 V), a lateral PNP transistor (h/sub FE/ of 51 and BV/sub CEO/ of 4.5 V), and NMOS and PMOS transistors (0.5 /spl mu/m channel length and 5 /spl mu/m channel width, 0.5/-0.8 V threshold voltage) am fabricated. This technology provides very promising low power, low cost, and high performance solutions for RF mixed-signal system-on-a-chip (SoC) applications.

Excellent cross-talk isolation, high-Q inductors, and reduced self-heating in a TFSOI technology for system-on-a-chip applications

In this paper, novel structures are reported to improve the cross-talk isolation, the performance of on-chip inductors, and the self-heating in a thin-film silicon-on-insulator (TFSOI) technology. In these structures, p/sup +/ substrate contact rings are used to improve the cross-talk isolation, appropriately doped TFSOI layers are used for high-Q inductors, and source contacts connected to the substrate are used to minimize the self-heating problem. The p/sup +/ substrate contact rings provide -57 dB isolation (typically characterized for a device spacing of 100 /spl mu/m) at 10 GHz, which is the best ever reported in TFSOI technology. A maximum Q-factor of 10.4 is obtained for TFSOI-layer shielded on-chip inductors. The inductor-to-inductor isolation is -62 dB (for a spacing of 100 /spl mu/m) at 10 GHz, which is close to the ideal isolation of the open probes. The source contacts connected to the substrate improves the self-heating by 16%. The excellent cross-talk isolation performance, high-Q on-chip inductors, and reduced self-heating make the TFSOI technology a very suitable candidate for mixed signal system-on-a-chip (SOC) applications.

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configurations pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.

A novel 3-D BiCMOS technology using selective epitaxy growth (SEG) and lateral solid phase epitaxial (LSPE)

In this paper, a novel three-dimensional (3-D) BiCMOS technology is proposed and demonstrated. In this technology, the NMOS transistor is fabricated on the bulk substrate (bottom layer) and the PMOS transistor is fabricated on the single-crystal top layer obtained using the selective epitaxy growth (SEG) and lateral solid phase epitaxy (LSPE). In addition, the BJT is fabricated in the SEG region. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than that of the PMOS fabricated on SOI, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and f/sub max/ of 14 GHz at V/sub ce/=3 V. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuit applications.

A 3-D BiCMOS technology using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)

In this paper, a novel 3-D BiCMOS technology is proposed and demonstrated for the first time. To implement the 3-D BiCMOS structure, NMOS transistors are fabricated on the bulk substrate (bottom layer), PMOS transistors are fabricated on the single crystal top layer which is obtained using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE), and BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than those fabricated on SOI wafers, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and a peak f/sub max/ of 14 GHz. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuits applications.

Novel isolation structures for TFSOI technology

In this letter, novel isolation structures are reported to improve the cross-talk isolation between active devices as well as the performance of on-chip inductors in a thin-film SOI (TFSOI) technology. In these structures, p/sup +/ substrate contact rings and appropriately doped TFSOI layers are used. The p/sup +/ substrate contact rings provides -57 dB isolation (typically characterized for a device spacing of 100 /spl mu/m) at 10 GHz, which is the best ever reported in TFSOI technology. A maximum Q-factor of 10.4 is obtained for TFSOI-layer shielded on-chip inductors. The inductor-to-inductor isolation is -62 dB (for a spacing of 100 /spl mu/m) at 10 GHz, which is close to the ideal isolation of the open probes. This excellent cross-talk isolation performance and the high-Q on-chip inductors make the TFSOI technology a very suitable candidate for mixed signal RF system-on-a-chip (SOC) applications.

A high-performance five-channel NMOSFET using selective epitaxial growth and lateral solid phase epitaxy

In this letter, a novel five-channel NMOSFET (FC-NMOS) using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE) is reported. The FC-NMOS is an integration of a conventional bulk NMOS, two vertical NMOS, and a gate-all-around NMOS. The top silicon layer for implementing the gate-all-around structure is obtained by using the LSPE with the SEG pillar as the silicon seed. The FC-NMOS has a 3.6/spl times/ higher current drive as compared to the conventional bulk NMOS. This makes the FC-NMOS very promising for VLSI/ULSI applications.

A simple, high performance complementary TFSOI BiCMOS technology with excellent cross-talk isolation and high-Q inductors for low power wireless applications

Recent growth in the portable wireless communication market and the push for a mixed-signal system-on-chip (SOC) approach means that TFSOI technology has been explored to provide low power, low cost, and high performance solutions (Reedy et al., 1999). The previously reported TFSOI BiCMOS technology is simple but needs performance improvement (Parke et al., 1992), and while another type needs a very complicated process (Huang et al., 1993). High performance SOI lateral BJTs were reported recently (Shino et al., 1998; Nii et al, 1999). However, they need special processes and are not CMOS compatible. To provide a mixed-signal system-on-chip solution, the technology should include low power CMOS devices, low noise BJT devices, and high Q-factor on-chip inductors. Furthermore, all of these devices should be properly isolated. This paper presents a simple, high performance complementary TFSOI BiCMOS technology with the best ever reported cross-talk isolation and high-Q inductors. This technology is very promising for low power, mixed-signal RF system-on-chip applications.