Robert Trzcinski

A 44GHz differentially tuned VCO with 4GHz tuning range in 0.12 /spl mu/m SOI CMOS

A differentially tuned VCO is fully integrated in a standard microprocessor 0.12 /spl mu/m SOI CMOS. A phase noise of -101.8dBc/Hz at 1MHz offset is measured with 7.5mW at 1.5V. The VCO tuning range is 9.8% from 40GHz to 44GHz. The output power is up to -6dBm after a single-stage buffer amplifier with 6mW at 1.5V.

CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration

This paper reports a thin wafer handling technology that is compatible to CMOS processing conditions to enable 3D integration and assembly with high throughput at low cost. Using pulsed ultraviolet (UV) radiation from excimer lasers, device wafers as thin as 50µm can be released from the temporary mechanical handler wafer in less than 1min. Bonding, adhesive, debonding and post debond clean processes were demonstrated. CMOS circuit test vehicles were shown to be compatible with this temporary bonding and debonding processes.

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

A complementary LC-VCO is integrated in a 65nm SOI process and is statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz and frequency tuning range is 6.14GHz or 9.05%. It achieves a phase noise of -106dBc/Hz at 10MHz offset and consumes 5.37mW from a 1.2V supply. The VCO yield is 94.7% for 70GHz operation.

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.

CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement

A mixed-signal circuits performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process variations. A current-controlled oscillators performance and device threshold voltages are cross-correlated using simulation and RF measurement. Up to 93.9% cross-correlation between oscillation frequency and device threshold voltage is obtained, and strong model-to-hardware correlation is observed through statistical analysis of simulation result and circuit measurement. The yield learning process of design, simulation, measurement, and statistical analysis is proposed

Performance Variations of a 66GHz Static CML Divider in 90nm CMOS

A 66GHz maximum operating clock frequency is measured for a 90nm CMOS static CML divide-by-2 with a 25.5mW latch power dissipation. Statistical self-oscillation frequency measurements exhibit a mean of 42.6 and 39.2GHz at 25degC and 85degC, and a 2.8GHz standard deviation. The mean dissipated power is 44.3mW at 1.4V, with a 2.2mW standard deviation

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipating 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power mm-wave digital and RF circuit capability

A 90-nm silicon-on-insulator (SOI) CMOS system on-chip integrates high-performance FETs with 243-GHz F/sub t/, 208-GHz F/sub max/, 1.45-mS//spl mu/m gm, and sub 1.1-dB NFmin up to 26 GHz. Inductor Q of 20, VNCAP of 1.8-fF//spl mu/m/sup 2/, varactor with a tuning range as high as 25:1, and a low-loss microstrip. Transmission lines were successfully integrated without extra masks and processing steps. SOI and its low parasitic junction capacitance enables this high level of performance and will expand the use of CMOS for millimeter-wave applications.

A 4-91 GHz distributed amplifier in a standard 0.12 /spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage distributed amplifiers (DA) in a 0.12 /spl mu/m SOI CMOS technology. The five-stage DA has a 4 to 91 GHz bandpass frequency with a gain of 5 dB. The seven-stage DA has a 5 to 86 GHz bandpass frequency with a gain of 9 dB. The power consumption is 90 and 130 mW for the 5-stage and 7-stage respectively at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm/sup 2/ for the 5-stage and 7-stage respectively.

Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configurations pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.