Choshu Ito

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.

RF ESD protection strategies: Codesign vs. low-C protection

The present work is focussed on the trade off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.

Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies

A design methodology and protection strategy for ESD charged-device-model (CDM) robust digital systems is presented using a scalable postbreakdown transistor macromodel for 90- and 130-nm technologies. The macromodel was implemented in a design tool to aid reliable chip design and used to predict function failure in three different system-on-chip design examples. Simulations agree well with failure analysis observations, verifying the validity of the macromodel. A ldquocorrect-by-constructionrdquo protection strategy for overcoming induced ESD-CDM events is also proposed. No ESD-CDM-related function failures are observed for product chips protected with this strategy.

Analysis and design of ESD protection circuits for high-frequency/RF applications

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high frequency and RF circuits. This work presents for the first time, an S-parameter based analysis of the performance of RF circuits with various ESD protection designs. Additionally, a design methodology for distributed ESD protection using coplanar waveguides is developed to achieve a better impedance match over a broad frequency range. By using this technique, an ESD device with a parasitic capacitance of 200 fF will attenuate the signal power by only 0.27 dB at 10 GHz.

Post-breakdown leakage resistance and its dependence on device area

Sub-nanosecond pulses were used to stress gate capacitors and the post-breakdown leakage resistance is analyzed. Post-breakdown leakage resistance obtained using sub-nanosecond pulse stress and ramp voltage stress are compared, and a power-law relationship between the inverse of the post-breakdown leakage resistance and device area is observed.

Gate oxide reliability characterization in the 100ps regime with ultra-fast transmission line pulsing system

An Ultra-fast Transmission Line Pulsing (UFTLP) system is demonstrated. Very short pulses down to 40 ps with a large voltage range (up to 100 V in this work) can be generated. Gate oxide reliability is quantified in the 100 ps regime for the first time. Hard and soft breakdown transitions are clearly captured, and the results explain why some logic cells still function after breakdown events.

Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events

A post-breakdown transistor macro-model for 90nm and 130nm technologies is presented and experimentally verified. Oxide breakdown does not necessarily imply function failure. The location of breakdown within the circuit is also important. A simulation methodology implementing this macro-model is presented. This tool can be used to predict function failure for three different system-on-chip (SoC) design examples. Simulations agree well with failure analysis (FA) observations, verifying the validity of the macro-model

Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applications

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This work presents a detailed s-parameter based analysis of the performance of these circuits with special attention to the distributed ESD protection designs. It has been shown that a 4-stage distributed ESD protection can be beneficial at frequencies greater than 3 GHz. Two generalized design optimization methodologies using coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range. By using this optimized design, an ESD device with a parasitic capacitance of 200 fF will attenuate the RF signal power by only 0.27 dB at 10 GHz. A design strategy is also suggested for high-speed mixed-signal ICs.

A New Methodology for Efficient and Reliable Large- Signal Analysis of RF Power Devices

In RF power device design, much of the analysis is based on measurements. Complete analysis by simulation is often avoided because the high-frequency, largesignal operation makes device simulation unsuitable, and the difficulties in obtaining a good physical compact model make circuit simulation inaccurate. This work presents a methodology that overcomes these limitations by utilizing a combination of device and circuit simulations to characterize large-signal operation of RF power devices quickly and accurately. Results show that circuit simulations using an extracted Root model agree well with device simulation for the intrinsic device. It is also demonstrated that changes in device design are reflected in circuit-level RF performance.