Tze Wee Chen

Gate-Oxide Early Life Failure Prediction

This paper uses 90nm transistor-level experimental data, device modeling, and circuit simulations to establish the following results: 1. A transistor with defective gate- oxide, i.e., a gate-oxide early-life failure (ELF) candidate transistor, produces gradually degraded drive currents over time before it completely loses its transistor characteristics; 2. The above phenomenon results in gradual increase in delays of digital circuit paths containing the ELF candidate transistor before the circuit produces functional failures; 3. Gradual delay shifts caused by ELF candidate transistors are large enough to be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through ELF identification during production test or on-line during system operation.

Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs

A synthesized compact modeling (SCM) approach for substrate coupling analysis is presented. The SCM is formulated using a scalable Z matrix approach for heavily doped substrates with a lightly doped epitaxial layer and using a nodal lumped resistance approach for lightly doped substrates. The SCM models require a set of process-dependent fitting coefficients and incorporate geometrical parameters of the substrate ports in a compact form that includes size, perimeter, and separation defined using the geometric mean distance to accommodate both far-field and near-field effects. The SCM approach is verified based on measurement data from two test chips, one in a custom lightly doped process and the other one using a 0.18-mum BiCMOS lightly doped foundry process. The model accuracy is shown to be within 15% compared to measured data extracted from the test patterns. The SCM is exploited with application examples to show substrate model generation efficiency and accuracy at different levels of complexity, including a full chip substrate noise distribution analysis for a 2 mm by 2 mm chip with 319 substrate contacts

Experimental study of gate oxide early-life failures

Large-scale experimental data from 90nm test chips consisting of 49,152 transistors, and experiments on 90nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences gradual delay shifts over time before the circuit produces functional failures. These results may be utilized to effectively overcome ELF challenges in scaled CMOS technologies.

ESD design challenges and strategies in deeply-scaled integrated circuits

Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and their applications in providing key information for reliability modeling are investigated. Package and wafer level CDM correlation issues are examined.

Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies

A design methodology and protection strategy for ESD charged-device-model (CDM) robust digital systems is presented using a scalable postbreakdown transistor macromodel for 90- and 130-nm technologies. The macromodel was implemented in a design tool to aid reliable chip design and used to predict function failure in three different system-on-chip design examples. Simulations agree well with failure analysis observations, verifying the validity of the macromodel. A ldquocorrect-by-constructionrdquo protection strategy for overcoming induced ESD-CDM events is also proposed. No ESD-CDM-related function failures are observed for product chips protected with this strategy.

Gate-oxide early-life failure identification using delay shifts

This paper presents experimental data from digital circuits on 90nm test chips, together with circuit simulations, to establish the following results: 1. The presence of a gate-oxide early-life failure (ELF) candidate transistor (also called infant mortality) in a logic gate results in delay shifts over time; 2. Delay shifts can be effective indicators of gate-oxide ELF suspects that may be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through effective ELF screening during production test or on-line during system operation for systems with built-in self-healing.

Post-breakdown leakage resistance and its dependence on device area

Sub-nanosecond pulses were used to stress gate capacitors and the post-breakdown leakage resistance is analyzed. Post-breakdown leakage resistance obtained using sub-nanosecond pulse stress and ramp voltage stress are compared, and a power-law relationship between the inverse of the post-breakdown leakage resistance and device area is observed.

Gate oxide reliability characterization in the 100ps regime with ultra-fast transmission line pulsing system

An Ultra-fast Transmission Line Pulsing (UFTLP) system is demonstrated. Very short pulses down to 40 ps with a large voltage range (up to 100 V in this work) can be generated. Gate oxide reliability is quantified in the 100 ps regime for the first time. Hard and soft breakdown transitions are clearly captured, and the results explain why some logic cells still function after breakdown events.

Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes

A synthesized compact model of substrate coupling resistance for lightly doped substrate processes is proposed. The model incorporates all geometrical parameters including geometrical mean distance with a few process-dependent fitting coefficients. The model accuracy is shown to be within 15% error using the measurement data from two test chips, one in a customized lightly doped process and the other one in a 0.18-/spl mu/m BiCMOS lightly doped process. Substrate noise distribution on a 2 mm by 2 mm chip with 319 substrate contacts is shown with the calibrated SCM model.

Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events

A post-breakdown transistor macro-model for 90nm and 130nm technologies is presented and experimentally verified. Oxide breakdown does not necessarily imply function failure. The location of breakdown within the circuit is also important. A simulation methodology implementing this macro-model is presented. This tool can be used to predict function failure for three different system-on-chip (SoC) design examples. Simulations agree well with failure analysis (FA) observations, verifying the validity of the macro-model