Chris Wrigley

A snap-shot CMOS active pixel imager for low-noise, high-speed imaging

Design and performance of a 128/spl times/128 snap-shot imager implemented in a standard single-poly CMOS technology is presented. A new pixel design and clocking scheme allow the imager to provide high-quality images without motion artifacts at high shutter speeds (<75 /spl mu/sec, exposure), with low noise (<5 e/sup -/), immeasurable image lag, and excellent blooming protection.

An enhanced-performance CMOS imager with a flushed-reset photodiode pixel

A new front-end for photodiode-based CMOS imagers is presented. Degradation in imaging performance due to conventional hard- and soft-reset of pixels is analyzed. To overcome these limitations, the design and operation of a flushed-reset pixel is described. The flushed-reset pixel combines the best of hard- and soft-reset to simultaneously provide excellent radiometric accuracy, high linearity, no image lag, high saturation level, and reduced read-noise. The new front-end is implemented by changes to the column-circuitry only, leaving the pixel unchanged, preventing degradation of any unrelated imaging performance. It is compatible with large format imager implementation, has minimal impact on the frame-rate, and does not introduce any additional hot-carrier stress in the pixel. Data from a large format (512/sup 2/) imager demonstrates the efficacy of the flushed-reset pixel approach.

Dynamically reconfigurable vision with high performance CMOS active pixel sensors (APS)

A high-performance computational imager based on integration of CMOS active pixel imager array with on-chip signal processing and control via a new column-parallel architecture is presented. Unlike CCDs and other CMOS imagers, the sensor is capable of providing simultaneous image data from three flexible, partially overlapping, dynamically reconfigurable regions of interest (ROIs) with different spatial resolution over a large field-of-view (FOV) to achieve data-efficient operation with high update rates. The power dissipation depends upon reconfiguration modes, but is small even in the worst case. Unlike conventional computational imagers, the integration of processing circuitry does not trade with radiometric accuracy, nor does it impose any limit to scaling the imager size to larger format and smaller pixels. By eliminating the need for mechanical pointing through floating-fovea support, the dynamically reconfigurable vision sensor (DSRVS) enables a low-power staring vision system. By maximizing system throughput through intelligent data reduction and through real-time programmability, it meets the diverse and conflicting requirements of search, identify and track vision-modes, and represents an efficient platform for high-bandwidth automatic target acquisition and tracking.

A single-chip programmable digital CMOS imager with enhanced low-light detection capability

The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, single-chip, digital camera systems. We report at fully digital, programmable, 5-wire, large format (512/spl times/512) camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The chip runs off a single (3.3 V) power supply, consumes only 10 mW, is capable of electronic panning, and produces high quality images with a low noise of <40 e/sup -/, and excellent response linearity down to read noise levels.

A low-power digital camera-on-a-chip implemented in CMOS active pixel approach

The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, integrated, single-chip camera systems. We report the first fully digital, programmable, 5-wire, large format (512/spl times/512) digital-camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The VLSI chip runs off a single (3.3 V) power supply, consumes only 8 mW at video rates, is capable of electronic panning, and produces high quality images with 78 dB dynamic range.

CMOS imager with charge-leakage compensated frame difference and sum output

This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames. Existing difference imagers are susceptible to errors due to collection (by the sense element and in-pixel storage node) of photo-generated charge that diffuses from the photo-active pixel area during integration of the second frame. This leakage cannot be removed in post-processing without frame rate reduction and additional frame memory penalties to readout and store the original frames. Our proof-of-concept imager uses a new unbalanced differential signal chain to provide 17 fold reduction in leakage error in the frame-difference output. The resulting residual error is <1.5% of the actual frame difference value, over >100x illumination range. Error reduction is achieved without noticeable fixed-pattern-noise (FPN) or random noise in the image, preserving high image quality. Power dissipation in the 256/spl times/256 imager is measured to be only 18 mW.

CMOS digital imager design from a system-on-a-chip perspective

Due to substantial mixed analog-digital circuit integration in one chip, CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binary-scaled tree-topology power routing has been shown to be critical for minimizing chip area and providing low spatial pattern noise. Imaging artifacts due to timing asymmetry have been quantified, and methods for elimination of the artifacts have been demonstrated. The impact of on-chip bias-generation and drive circuits on the on-chip ADC performance has been shown. New timing and circuit layout techniques have been presented for enabling random noise limited performance of a CMOS imager.