Monico Ortiz

Reset noise suppression in two-dimensional CMOS photodiode pixels through column-based feedback-reset

We present a new CMOS photodiode imager pixel with ultralow read noise through on-chip suppression of reset noise via column-based feedback circuitry. In a 0.5 /spl mu/m CMOS process, the pixel occupies only 10/spl times/10 /spl mu/m/sup 2/ area. Data from a 256/sup 2/ CMOS imager indicates imager operation with read noise as low as 6 electrons without employing on- or off-chip correlated double sampling. The noise reduction is achieved without introducing any image lag, and with insignificant reduction in quantum efficiency and full-well.

A single-chip programmable digital CMOS imager with enhanced low-light detection capability

The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, single-chip, digital camera systems. We report at fully digital, programmable, 5-wire, large format (512/spl times/512) camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The chip runs off a single (3.3 V) power supply, consumes only 10 mW, is capable of electronic panning, and produces high quality images with a low noise of <40 e/sup -/, and excellent response linearity down to read noise levels.

A low-power digital camera-on-a-chip implemented in CMOS active pixel approach

The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, integrated, single-chip camera systems. We report the first fully digital, programmable, 5-wire, large format (512/spl times/512) digital-camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The VLSI chip runs off a single (3.3 V) power supply, consumes only 8 mW at video rates, is capable of electronic panning, and produces high quality images with 78 dB dynamic range.

CMOS imager with charge-leakage compensated frame difference and sum output

This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames. Existing difference imagers are susceptible to errors due to collection (by the sense element and in-pixel storage node) of photo-generated charge that diffuses from the photo-active pixel area during integration of the second frame. This leakage cannot be removed in post-processing without frame rate reduction and additional frame memory penalties to readout and store the original frames. Our proof-of-concept imager uses a new unbalanced differential signal chain to provide 17 fold reduction in leakage error in the frame-difference output. The resulting residual error is <1.5% of the actual frame difference value, over >100x illumination range. Error reduction is achieved without noticeable fixed-pattern-noise (FPN) or random noise in the image, preserving high image quality. Power dissipation in the 256/spl times/256 imager is measured to be only 18 mW.