Christian Bachmann

Low-power wireless sensor nodes for ubiquitous long-term biomedical signal monitoring

In the past few years, the use of wireless sensor nodes for remote health care monitoring has been advocated as an attractive alternative to the traditional hospital-centric health care system from both the economic perspective and the patient comfort viewpoint. The semiconductor industry plays a crucial role in making the changes in the health care system a reality. User acceptance of remote health monitoring systems depends on their comfort level, among other factors. The comfort level directly translates to the form factor, which is ultimately defined by the battery size and system power consumption. This article introduces low-power wireless sensor nodes for biomedical applications that are capable of operating autonomously or on very small batteries. In particular, we take a closer look at component-level power optimizations for the radio and the digital signal processing core as well as the trade-off between radio power consumption and on-node processing. We also provide a system-level model for WSNs that helps in guiding the power optimization process with respect to various trade-offs.

13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS

This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mW for RX and 4.4mW for TX.

10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks

Ultra-low-power (ULP), short-range wireless connectivity is becoming increasingly relevant to a wide range of sensor and actuator node applications, ranging from consumer lifestyle to medical applications. In recent years, a multitude of wireless standards has been proposed to meet differing requirements of individual application domains such as data rates, range, QoS, peak and average power consumption. From a commercial perspective, a single radio component that is capable of supporting multiple wireless standards - targeting multiple application domains/markets - while reducing integration costs is highly preferable. At the same time, the multi-standard support may not compromise low-power operation or silicon area.

26.3 A 1.3nJ/b IEEE 802.11ah fully digital polar transmitter for IoE applications

This paper presents an ultra-low-power (ULP) IEEE 802.11ah fully-digital polar transmitter (TX). IEEE 802.11ah is a new Wi-Fi protocol optimized for Internet-of-Everything (IoE) applications. Compared to other IoE standards like Bluetooth or ZigBee, its sub-GHz carrier frequency and mandatory modes with 1MHz/2MHz channel bandwidths allow devices to operate in a longer range with scalable data-rates from 150kb/s to 2.1Mb/s. Moreover, the use of OFDM improves link robustness against fading, especially in urban environments, and achieves a higher spectral efficiency. The key design challenges of an IEEE 802.11ah TX for IoE applications are to meet the tight spectral mask and error-vector-magnitude (EVM) requirements as for conventional Wi-Fi standards (e.g., 802.11n/g), while achieving low power consumption required by IoE applications. The presented TX applies a fully-digital polar architecture with a 1V supply, and it achieves more than 10× power reduction compared to the state-of-the-art OFDM transceivers [1-4]. Without any complicated PA pre-distortion techniques as in [5], it passes all the PHY requirements of the mandatory modes in IEEE 802.11ah with 4.4% EVM, while consuming 7.1mW with 0dBm output power.

A 1.3 nJ/b IEEE 802.11ah Fully-Digital Polar Transmitter for IoT Applications

A 1.3 nJ/b IEEE 802.11ah TX for IoT applications is presented. A fully-digital polar architecture consisting of an all-digital PLL-based frequency modulator and an AM-retiming ΔΣ switched-capacitor PA (SC-PA) achieves more than 10× power reduction than state-of-the-art OFDM TXs. Several circuit-design techniques such as LSB truncation error feedback are proposed to efficiently pre-process the AM/PM data to improve the TX performance. A design approach of the SC-PA for optimum overall efficiency is introduced. The PLL spur level is reduced to 55 dBc by a switched-capacitor based digital-to-time converter. A dynamic divider is implemented together with a 1.8 GHz oscillator for efficient LO generation. Fabricated in a 40 nm CMOS process, this TX fulfills all the IEEE 802.11ah mandatory-mode PHY requirements with 4.4% EVM and > 4.8 dB spectral mask margin, while consuming 7.1 mW from a 1 V supply when delivering 0 dBm output power.

A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS

An energy-efficient, flexible radio SoC with RF front-end (RFFE), digital baseband (DBB) and microcontroller (MCU) for medical/healthcare applications in 315/400 MHz bands is presented. The SoC is fully-compliant with the IEEE 802.15.6 standard in 400MHz bands, and also supports proprietary modes, including high data rate (HDR) modes with x2/4/8 data rates (max 3.6Mb/s) to support applications like EEG, and low-power modes with 1/16 data rate to minimize sensor node power consumption. The total power consumption of 3.5mW (RX, 3.6Mb/s, −77dBm sensitivity) enables best-in-class power efficiency of 1nJ/bit.

A 4mW-RX 7mW-TX IEEE 802.11ah fully-integrated RF transceiver

An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this receiver achieves −104dBm sensitivity in the 1MHz MCS0 mode (i.e., 300kbp/s). It fulfils the adjacent channel rejection requirements with at least 17dB margin. The digital polar transmitter achieves −31dB EVM and 10dB spectral mask margin.

17.4 A sub-mW antenna-impedance detection using electrical balance for single-step on-chip tunable matching in wearable/implantable applications

Wearable/implantable devices, e.g., heart-rate-monitor straps and implanted wireless sensors, need to be ultra-low-power (ULP), compact, and also robust against the proximity effect, which can significantly degrade the antenna and front-end performance and hence battery lifetime. A fully integrated adaptive front-end with a tunable matching network (TMN) using low-power and fast impedance detection is highly desirable for robust and efficient operation.

A 2.4GHz BLE-compliant fully-integrated wakeup receiver for latency-critical IoT applications using a 2-dimensional wakeup pattern in 90nm CMOS

This paper presents a wakeup receiver for latency-critical IoT applications in 90nm CMOS, which is fully compliant to many popular IoT wireless standards with constant envelope modulations, such as Bluetooth Low Energy and IEEE802.15.4. Paired with a standard-compliant transmitter, the proposed wakeup receiver method minimizes the overhead in system power, area and complexity. The proposed 2-dimensional wakeup pattern reduces the latency of a wakeup event to below 100µs. Supplied at a battery voltage of 2V, the chip fully integrates a power management unit, a wakeup receiver with offset and noise suppression, a low power digital baseband with automatic gain control and RSSI estimation, and a crystal oscillator. With a BLE compliant signal, the chip achieves −58dBm sensitivity, and a >600s mean time without false alarm, consuming 195µA.

5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load

Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (XO) generates a stable reference clock for the PLL to synthesize a carrier and to derive clocks for all other parts of the transceiver SoC, e.g., ADC and the digital baseband. The typical start-up time (Ts) of an XO is relatively long (∼ms) due to a high quality factor of the crystal quartz. This leads to a significant (up to 30%) power overhead for a highly duty-cycled transceiver with a short packet format, e.g., the packet length is as short as 128µs in BLE (Fig. 5.3.1). A reduction of Ts of the XO is necessary, at the same time, the power overhead to enable a fast start-up should be minimized in order to reduce the overall energy consumption (Fig. 5.3.1).