Christian Benkeser

Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm2 radix-4based 8× parallel turbo-decoder ASIC in 0.13 μm CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.

Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems

Turbo decoders for modern wireless communication systems have to support high throughput over a wide range of code rates. In order to support the peak throughputs specified by modern standards, parallel turbo-decoding has become a necessity, rendering the corresponding VLSI implementation a highly challenging task. In this paper, we explore the implementation trade-offs of parallel turbo decoders based on sliding-window soft-input soft-output (SISO) maximum a-posteriori (MAP) component decoders. We first introduce a new approach that allows for a systematic throughput comparison between different SISO-decoder architectures, taking their individual trade-offs in terms of window length, error-rate performance and throughput into account. A corresponding analysis of existing architectures clearly shows that the latency of the sliding-window SISO decoders causes diminishing throughput gains with increasing degree of parallelism. In order to alleviate this parallel turbo-decoder predicament, we propose a new SISO-decoder architecture that leads to significant throughput gains and better hardware efficiency compared to existing architectures for the full range of code rates.

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

In this paper, we investigate the impact of circuit misbehavior due to parametric variations and voltage scaling on the performance of wireless communication systems. Our study reveals the inherent error resilience of such systems and argues that sufficiently reliable operation can be maintained even in the presence of unreliable circuits and manufacturing defects. We further show how selective application of more robust circuit design techniques is sufficient to deal with high defect rates at low overhead and improve energy efficiency with negligible system performance degradation.

Implementation Trade-Offs of Soft-Input Soft-Output MAP Decoders for Convolutional Codes

Soft-input soft-output (SISO) maximum a-posteriori (MAP) decoders for convolutional codes (CCs) are an integral part of many modern wireless communication systems. Specifically, SISO-MAP decoding forms the basis for turbo decoders, as, e.g., specified for HSDPA or 3GPP-LTE, or for iterative detection and decoding in multiple-input multiple-output wireless systems, such as IEEE 802.11n. In this paper, we investigate the silicon-area, throughput, and energy-efficiency trade-offs associated with SISO-MAP decoders based on the algorithm developed by Bahl, Cocke, Jelinek, and Raviv (BCJR). To this end, we develop radix-2 and radix-4 architectures for high-throughput SISO-MAP decoding of CCs having 4, 8, 16, 32, and 64 states and present corresponding implementation results in 180 nm, 130 nm, and 90 nm CMOS technology. We validate technology-scaling rules and finally demonstrate the use of the presented trade-off analysis by identifying the key design parameters for parallel turbo-decoder implementations.

VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter

One of the key tasks in cognitive radio and communications intelligence is to detect active bands in the radio-frequency (RF) spectrum. In order to perform spectral activity detection in wideband RF signals, expensive and energy-inefficient high-rate analog-to-digital converters (ADCs) in combination with sophisticated digital detection circuitry are typically used. In many practical situations, however, the RF spectrum is sparsely populated, i.e., only a few frequency bands are active at a time. This property enables the design of so-called analog-to-information (A2I) converters, which are capable of acquiring and directly extracting the spectral activity information at low cost and low power by means of compressive sensing (CS). In this paper, we present the first very-large-scale integration (VLSI) design of a monolithic wideband CS-based A2I converter that includes a signal acquisition stage capable of acquiring RF signals having large bandwidths and a high-throughput spectral activity detection unit. Low-cost wideband signal acquisition is obtained via CS-based randomized temporal subsampling in combination with a 4-bit flash ADC. High-throughput spectrum activity detection from the coarsely quantized and compressive measurements is achieved by means of a massively-parallel VLSI design of a novel accelerated sparse spectrum dequantization (ASSD) algorithm. The resulting monolithic A2I converter is designed in 28 nm CMOS, acquires RF signals up to 6 GS/s, and the on-chip ASSD unit detects the active RF bands at a rate 30 × below real-time.

Data mapping for unreliable memories

Future digital signal processing (DSP) systems must provide robustness on algorithm and application level to the presence of reliability issues that come along with corresponding implementations in modern semiconductor process technologies. In this paper, we address this issue by investigating the impact of unreliable memories on general DSP systems. In particular, we propose a novel framework to characterize the effects of unreliable memories, which enables us to devise novel methods to mitigate the associated performance loss. We propose to deploy specifically designed data representations, which have the capability of substantially improving the system reliability compared to that realized by conventional data representations used in digital integrated circuits, such as 2s-complement or sign-magnitude number formats. To demonstrate the efficacy of the proposed framework, we analyze the impact of unreliable memories on coded communication systems, and we show that the deployment of optimized data representations substantially improves the error-rate performance of such systems.

Turbo decoder design for high code rates

Turbo decoders for modern wireless communication systems are required to support a wide range of code rates. The maximum supported code rate has strong impact on the choice of turbo decoder algorithm and architecture. This paper explores the problem of achieving high performance with turbo decoders at high code rates, and provides solutions on algorithmic and architectural level. A standard-compliant turbo decoder ASIC prototype for 3GPP Evolved EDGE has been implemented in 0.18 μm CMOS, and corresponding measurements proof the results of our analysis.

Efficient channel shortening for higher order modulation: Algorithm and architecture

Trellis-based channel equalization for GSM/EDGE with 8PSK modulation requires pre-filtering to achieve high performance at acceptable complexity. Since corresponding implementation complexity grows with modulation order, the introduction of 16/32QAM in the latest 2G standard Evolved EDGE requires new solutions to preserve the low-cost attribute of EDGE-enabled devices. This paper describes a novel efficient pre-filter algorithm based on homomorphic filtering. The corresponding hardware implementation in 130 nm CMOS achieves a 5× improvement of area-timing (AT-)product when compared to prior art.

A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End

A multimode digital front-end for EDGE, WCDMA, and WLAN modes and a WCDMA/HSDPA receiver is implemented in 0.13mum 1P6M CMOS technology occupying 5.15mm2 and dissipating 0.8/48/31 mW in EDGE/HSDPA/WLAN modes, respectively.

A 390Mb/s 3.57mm 2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS

Recent popularity of smart phones, netbooks, and other mobile broadband devices has vindicated 3G (WCDMA/HSPA) as an enabling technology for mainstream high-speed data and has given fresh impetus to its 4G successor, LTE (Long-Term Evolution). With mass deployment anticipated in 2-to-3 years, development of cost-effective and low-power LTE user equipment is currently keeping the wireless industry preoccupied. While the 1st-generation terminals will target 100Mb/s in the downlink, the MIMO-based LTE standard is capable of 326.4Mb/s [1] operation, which is more than 20× that of HSDPA. As with HSDPA, turbo decoding will be among the challenges (along with MIMO detection) in computation intensity, now threatening to be 20× higher. This contribution explores the feasibility of achieving the LTE maximum throughput with a turbo decoder ASIC realization, and the 100Mb/s milestone with competitive power consumption and die area.