David E. Bellasi

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing

Sparse signal recovery finds use in a variety of practical applications, such as signal and image restoration and the recovery of signals acquired by compressive sensing. In this paper, we present two generic very-large-scale integration (VLSI) architectures that implement the approximate message passing (AMP) algorithm for sparse signal recovery. The first architecture, referred to as AMP-M, employs parallel multiply-accumulate units and is suitable for recovery problems based on unstructured (e.g., random) matrices. The second architecture, referred to as AMP-T, takes advantage of fast linear transforms, which arise in many real-world applications. To demonstrate the effectiveness of both architectures, we present corresponding VLSI and field-programmable gate array implementation results for an audio restoration application. We show that AMP-T is superior to AMP-M with respect to silicon area, throughput, and power consumption, whereas AMP-M offers more flexibility.

VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter

One of the key tasks in cognitive radio and communications intelligence is to detect active bands in the radio-frequency (RF) spectrum. In order to perform spectral activity detection in wideband RF signals, expensive and energy-inefficient high-rate analog-to-digital converters (ADCs) in combination with sophisticated digital detection circuitry are typically used. In many practical situations, however, the RF spectrum is sparsely populated, i.e., only a few frequency bands are active at a time. This property enables the design of so-called analog-to-information (A2I) converters, which are capable of acquiring and directly extracting the spectral activity information at low cost and low power by means of compressive sensing (CS). In this paper, we present the first very-large-scale integration (VLSI) design of a monolithic wideband CS-based A2I converter that includes a signal acquisition stage capable of acquiring RF signals having large bandwidths and a high-throughput spectral activity detection unit. Low-cost wideband signal acquisition is obtained via CS-based randomized temporal subsampling in combination with a 4-bit flash ADC. High-throughput spectrum activity detection from the coarsely quantized and compressive measurements is achieved by means of a massively-parallel VLSI design of a novel accelerated sparse spectrum dequantization (ASSD) algorithm. The resulting monolithic A2I converter is designed in 28 nm CMOS, acquires RF signals up to 6 GS/s, and the on-chip ASSD unit detects the active RF bands at a rate 30 × below real-time.

A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes

In wireless sensor nodes with a tight power budget, minimizing both the amount of transmitted data and the complexity of the algorithms used for data compression are fundamental in achieving long battery life-time. Compressed Sensing (CS) has been proposed to process incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. We show that the architecture implementing parallel projection-based CS can be reused to realize a linear estimator able to minimize the transmitted data when the primary interest is the acquisition of a scalar feature of the signal rather than its entire profile. Further, we increase the energy-efficiency of the architecture by puncturing the sample stream which allows the duty-cycle of both the analog front-end and the analog-to-digital converter to be reduced. We found that conventional CS acquisition can be made more energy-efficient as it tolerates a certain amount of random puncturing, and also that more substantial power savings can be achieved when estimation is the target and undersampling is optimized by a suitable algorithm. In the latter case, the power consumption of all circuit blocks in the signal chain can be reduced by more than one order of magnitude with respect to the standard solution that samples and transmits raw data for off-board processing. The effectiveness of optimized undersampling is demonstrated in two case studies; first, the estimation of the amplitude of an electrical signal, and second, the estimation of the maximum solar radiation measured by a real-world sensor.

A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS

Spectral activity detection in wideband radio-frequency (RF) signals for cognitive-radio applications typically necessitates expensive and energy-inefficient analog-to-digital converters (ADCs). In this paper, we present a novel compressive sensing (CS)-based analog front-end, which is able to sample sparse wideband RF signals at low cost and low power. The analog front-end consists of a pseudo-random non-uniform clock generator unit offering the possibility to configure the (average) undersampling factor at run-time, and a low-cost, wideband 1.9 GS/s 4-bit flash ADC. The spectral information acquired at sub-Nyquist rates can be recovered off-line via novel sparse signal dequantization algorithms. The developed analog front-end is implemented in 28nm CMOS, and enables the recovery of spectrally sparse RF signals up to 3.8 GHz by means of CS, which corresponds to a Nyquist-equivalent sampling rate of 7.6 GS/s. The ADC and pseudo-random clock generator together occupy less than 0.1mm2, and consume an estimated 4.1mW to 5.4mW for undersampling factors between 4 and 11.5.

A wide tuning-range ADFLL for mW-SoCs with dithering-enhanced accuracy in 65 nm CMOS

We present an integer-N all-digital frequency-locked loop (ADFLL) suitable for dynamic voltage and frequency scaling in system-on-chips targeting mW-consumption. The proposed ADFLL operates with a 32 kHz clock reference, and offers a large clock multiplication factor of 32786, resulting in a wide tuning-range from 19 kHz to 1.048 GHz at 1.2 V and to 250 MHz at 0.8 V,. It incorporates a jitter reduction technique enabling the generation of accurate low-rate clocks in ADFLLs, combining clock division and dithering based on a 1st-order digital ΣΔ-modulator. The measured clock division factor dependent reduction of the peak cycle-to-cycle (C2C) jitter was between 40% and 70% at a 200 MHz DCO clock. The lowest peak C2C jitter of 0.14% was measured at a 3.15MHz output clock derived from a 800 MHz DCO clock. A prototype in UMC 65 nm CMOS occupies 0.013 mm2 of area, and at 100 MHz consumes 605 μW (scaling with 3 μW/MHz) at 1.2 V, and 205 μW (scaling with 1.2 μW/MHz) at 0.8 V.

An architecture for low-power compressed sensing and estimation in wireless sensor nodes

Radio communication is among the most energy consuming tasks in wireless sensor nodes. Reducing the amount of data to be transmitted holds a large power saving potential. The combination of compressed sensing (CS) and local signal parameter estimation can achieve a massive data rate reduction in applications where the primary interest is in the acquisition of a scalar feature of the signal rather than the reconstruction of the entire waveform. In this paper, We propose a compressed estimator, building upon an enhancement of the typical CS signal-modulation scheme via punctured sampling. Specifically, a subset of signal samples and associated weighting coefficients are chosen so as to minimize node power consumption while achieving a given estimation performance. We detail a corresponding puncturing algorithm and present the design of an integrated digital compressed estimation unit in 28nm FDSOI CMOS. In a concrete case study, local estimation combined with subsampling is shown to result in a power reduction of up to an order of magnitude with respect to the standard solution of sampling and transmitting samples for off-board processing.

Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS

Duty-cycled low-rate Internet-of-things (IoT) sensors are employed in diverse applications, requiring configurable and energy-efficient on-chip and on-demand clock synthesis. We present an all-digital frequency-locked loop (AD-FLL) capable of generating an accurate clock selectively in stand-alone operation or locked to a 32kHz reference. We report measurement results of two prototypes in 65nm and 28nm CMOS offering a configurable clock multiplication factor of up to 32 786, resulting in a wide tuning-range from a few MHz to 2.4GHz and 1.6GHz, respectively. The challenges of slow start-up and deterministic jitter are addressed by a fast hybrid-mode start-up procedure and by various jitter reduction modes. We also introduce the concept of Transient Clocking that leverages the capabilities of the proposed AD-FLL to make a system operational after cold-start or wake-up before the supply voltage has stabilized. We study two application examples that highlight the versatility of the concept in IoT applications and show its potential to amortize the time and energy cost of typical system start-up tasks, like state-restoration or wake-up event classification.

A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD

Wide-bandwidth lossless current sensors are critical in numerous applications, from current monitoring in DC-DC converters to non-invasive load monitoring. CMOS Hall sensor is a low-cost solution for current sensing and can be easily integrated as part of mixed-signal system-on-chips (SoCs). State-of-the-art CMOS Hall sensors offer only limited acquisition bandwidths of a few hundred kHz. This paper presents a 1 MHz Hall current sensor SoC integrating a broadband CMOS Hall sensor, two 2 MS/s ADCs and a multi-mode digital compressive sensing encoder for data rate reduction. The complete SoC is implemented in a STM 0.16 μm BCD technology, and occupies 16 mm2 while consuming less than 94 mW at 1.8 V.

Live demonstration: Real-time audio restoration using sparse signal recovery

We demonstrate the restoration of audio signals corrupted by clicks and pops using techniques from sparse signal recovery and compressive sensing. The demonstration features real-time signal restoration using the approximate message passing algorithm on an FPGA prototyping board. To highlight the restoration performance of our implementation, we remove clicks and pops from old phonograph recordings in real time.