Christian Dufaza

Digital oscillation-test method for delay and stuck-at fault testing of digital circuits

Testing delay faults is becoming critical in new deep submicron digital circuits. This paper introduces a new technique for delay and stuck-at fault testing in digital integrated circuits. The proposed technique consists of sensitizing a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all or at least critical paths in the circuit. To establish oscillations, we should make sure that there is an odd number of inverters in the loop. This technique can be used along with scan techniques or be implemented as a built-in self-test technique. Benchmark results confirm the efficiency of the proposed technique. The technique has been implemented in practice for an an 8-bit digital adder on a field programmable device.

Test synthesis for DC test and maximal diagnosis of switched-capacitor circuits

This paper presents a DFT/BIST technique for switched-capacitor (SC) circuits that consists of measuring all capacitance ratios of transfer functions in the DC domain. Then, the specifications of a SC circuit are computed from these measured capacitance ratios and compared to the fault-free ones. Moreover a maximal fault diagnosis is realized for the capacitances. This test technique uses re-configurations of the circuit so as that all the capacitance ratios are measured one by one at the different operational amplifiers outputs of the circuit. For this purpose, a standardized re-configuration of the three capacitances types, switched, un-switched and integrating capacitances, is described. Then, a test synthesis algorithm based on the fluency graph description of SC circuits is proposed and offers a formal approach to automate the technique. Finally, some recommendations concerning the design of the extra switches are given and simulations prove the low performance degradation of the circuit in test mode.

BIST linear generator based on complemented outputs

Autonomous linear finite state machines with both complemented and uncomplemented register outputs (mixed-output ALFSMs) have been investigated for their use as deterministic and pseudo-random test vector generators in a BIST scheme. The authors describe a method for deriving the feedback connections of the mixed-output ALFSM given a deterministic sequence of n n-bit wide test vectors. They also show that the state graph structure is preserved thus enabling the generation of maximum-length sequences if the characteristic polynomial of the connectivity matrix is primitive. An example is given to illustrate the synthesis method of a mixed-output ALFSM based test vector generator. A better solution is obtained compared to conventional uncomplemented output ALFSM.<<ETX>>

A BIST-DFT technique for DC test of analog modules

Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.

Theoretical properties of LFSRs for built-in self test

Linear Feedback Shift-Registers have been studied for a long time as interesting solutions for error detection and correction techniques in transmissions. In the test domain, and principally in Built-In Self Test applications, they are often used as generators of pseudo-random test sequences. Conversely, their potential to generate prescribed deterministic test sequences is dealt within more recent works, and nowadays, allows the investigation of efficient test with a pseudo-deterministic BIST technique. Pseudo-deterministic test sequences are composed of both deterministic and pseudo-random test patterns and offer high fault coverage with a tradeoff between test length and hardware cost. In this paper, synthesis techniques for LFSRs that embed such kind of sequences are described.

LFSROM an algorithm for automatic design synthesis of hardware test pattern generator

The characteristic of the on-chip test pattern generator (TPG) is of prime importance for the overall quality of the test of a circuit with built-in self-test (BIST). The authors describe in this paper a new TPG architecture which is basically composed of a shift register (SR), an OR gate network and a set of multiplexers. It is called a LFSROM and it can be easily designed in a relatively short time for even large test sets. The design synthesis algorithm is described in a step-by-step way by use of a real example so as to show clearly the key parameters to be considered in the design of such an architecture. Furthermore, the silicon area of the LFSROM has been found to be smaller than that of a ROM for the example considered.<<ETX>>

Design and experimental results of a built-in voltage sensor for mixed signal testing

Among test techniques for analog circuits, DC test is one of the simplest methods for BIST application since it is easy to integrate the test pattern generator but also the response analyzer. This paper presents such a technique and focuses on the design and the experimental results obtained with a Built-In Voltage Sensor that corresponds in our proposal to the analyzer module. Since this sensor gives directly a logical value, simple or multiple DC observation points can easily guarantee at low cost a maximal fault coverage detection. Experimental results obtained on an integrated chip validate the efficiency and the simplicity of this technique. Finally, the sensitivity of this sensor to process variations, temperature and power supply is discussed.

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors

Autonomous Linear Finite State Machines with both complemented and uncomplemented register outputs (Mixed-Output ALFSMs) have been investigated for their use as Deterministic and Pseudo-random Test Vector Generators in a BIST scheme. We describe herein, a method for deriving the feedback connections of the Mixed-Output ALFSM given a deterministic sequence of n n-bit wide test vectors. We also show that the state graph structure is preserved thus enabling the generation of maaimum-length sequences if the characteristic polynomial of the connectivity matrix is primitive.