Christian Hecht

Epitaxial Growth of n-Type 4H-SiC on 3" Wafers for Power Devices

In this paper we present recent results of epitaxial growth of 4H-SiC on 3” (0001) 8° and 4° off-oriented wafers using a multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5x3” or 7x2” wafers per run. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity in doping and thickness were grown. The intra-wafer as well as the wafer-to-wafer homogeneity will be illustrated by doping and thickness mappings of a full-loaded run. Surface morphology of epitaxial layers on 8° and 4° off-oriented wafers was investigated by atomic force microscopy.

High-Performance Multi-Wafer SiC Epitaxy – First Results of Using a 10x100mm Reactor

In this paper, we present first results of epitaxial layer deposition using a novel warm-wall CVD multi-wafer system AIX 2800G4 WW from AIXTRON with a capability of processing 10x100mm wafers per run. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 10x100mm runs will be shown and compared to results of the 6x100mm setup of our hot-wall reactor VP2000HW by AIXTRON used for device production since 2001.

Thick Epitaxial Layers on 4º Off-Oriented 4H-SiC Suited for PiN-Diodes with Blocking Voltages above 6.5 kV

This work presents results on the growth of thick epitaxial layers on 4° off-oriented 4HSiC in a commercially available hot-wall CVD system. Results on background doping level, homogeneity of thickness and doping, and run-to-run reproducibility will be shown. Defect structures we observed on 4° off-oriented substrates only are discussed. AFM measurements are presented to show the degree of step-bunching. 6.5 kV PiN-diodes with an active device area of 5.7 mm2 were fabricated and electrically characterized. In spite of the surface defects and stepbunching, up to 50% of the devices per wafer fulfilled our strict yield criteria even at 6.5 kV. Up to the onset of avalanche, the devices exhibited extremely low leakage currents. These results turn the cheaper 4° off-oriented substrates into a promising choice for producing higher volumes of highvoltage SiC power devices at reasonable costs.

Large-Area Homoepitaxial Growth of Low-Doped Thick Epilayers for Power Devices with VBR > 4 kV

In this paper we present results on the growth of low-doped thick epitaxial layers on 4° off-oriented 4H-SiC using a commercially available hot-wall multi-wafer CVD system. For the first time we show results of a low-doped full-loaded 73” run on 4° off-oriented substrates with a layer thickness of more than 70 µm. The target doping concentration of 1.2×1015 cm-3 is suitable for blocking voltages > 6 kV. Results on doping, thickness and wafer-to-wafer homogeneities are shown. The surface quality of the grown layers was characterized by AFM. The density of different types of dislocations was determined by Defect Selective Etching.

Challenges in Large-Area Multi-Wafer SiC Epitaxy for Production Needs

The rapid market development for SiC-devices during the last years can be attributed particularly to the success in supplying high-quality SiC wafers and corresponding epitaxial layers. The device quality could be enhanced and the costs were reduced by enlarging the wafer size as well as by a significant progress in epitaxial growth of active layers by using multi-wafer CVD systems. In this paper we want to give an overview of CVD multi-wafer systems used for SiC growth in the past and today. We present recent results of SiC homoepitaxial growth using our multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5×3” wafers per run and can be upgraded to a 7×3” or 5×4” setup. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity of doping and thickness have been grown. Issues like reproducibility, drift of parameters and system stability over several runs will be discussed.

SXRT Investigations on Electrically Stressed 4H-SiC PiN Diodes for 6.5 kV

4H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.

Influence of Epilayer Thickness and Structural Defects on the Minority Carrier Lifetime in 4H-SiC

4H-SiC homoepitaxial layers with different thicknesses from 12.5 µm up to 50 µm were investigated by microwave-detected photoconductivity decay (µ-PCD), deep level transient spectroscopy (DLTS) and defect selective etching (DSE) to shed light on the influence of the epilayer thickness and structural defects on the effective minority carrier lifetime. It is shown that the effective lifetime, resulting directly from the µ-PCD measurement, is significantly influenced by the surface recombination lifetime. Therefore, an adequate correction of the measured data is necessary to determine the bulk lifetime. The bulk lifetime of these epilayers is in the order of several microseconds. Furthermore, areas with high dislocation density are correlated to areas with locally reduced effective lifetime.

Epitaxial Growth of 4H-SiC on (000-1) C-Face Substrates by Cold-Wall and Hot-Wall Chemical Vapor Deposition

Epitaxial layers have been grown on the (0001) C-face of 2- and 3-inch 4H-SiC wafers. Growth conditions like temperature, pressure, and C/Si ratio have been varied. In both systems smooth surface morphologies could be obtained. The main challenge of epitaxial growth on the Cface of 4H-SiC for electronic device applications seems to be the control of low doping concentration. High temperature and low pressure are the key parameters to reduce the nitrogen incorporation. The hot-wall CVD system used for these experiments allowed the application of higher temperatures and lower pressures than the cold-wall equipment. The lowest doping concentration of 2.5x1015 cm-3 has been achieved by hot-wall epitaxy using a temperature of 1625 °C, a system pressure of 50 hPa, a C/Si ratio of 1.4, and a growth rate of 6.5 2mh-1. Good doping homogeneity on 2-inch and 3-inch wafers could be achieved. For a doping level of ND-NA= 3×1015 cm-3 sigma is about 15%.

High Voltage SiC Vertical JFET for High Power RF Applications

We present the optimization of a standard lateral channel vertical JFET for high-frequency high-power applications. It will be shown that SiC JFETs are well suited to fulfill the requirements of certain RF applications when compared to silicon devices. Simulations covering the electrical characteristics will be given together with calculations considering the self-heating of the chip in pulsed-power applications and the corresponding decrease in saturation current. The gate-signal propagation will be analyzed for different chip layouts and the effect on switching speed will be described. Electrical results will demonstrate that the optimized JFET is suitable for RF-transmitter applications, like e.g. solid state RF modules as Klystron replacements in linear accelerators.

Advances in Multi- and Single-Wafer SiC Epitaxy for the Production and Development of Power Diodes

In this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 7×3” or 6×100mm wafers per run in a new 100mm setup. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm and 7×3” runs will be shown. Results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3”, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.