Christie R. K. Marrian

Low voltage electron beam lithography in self‐assembled ultrathin films with the scanning tunneling microscope

With a scanning tunneling microscope (STM) operating in vacuum, we have studied the lithographic patterning of self‐assembling organosilane monolayer resist films. Where the organic group is benzyl chloride, the resist layer can be patterned with electrons down to 4 eV in energy. The patterned films have been used as templates for the electroless plating of thin Ni films. Linewidths down to ∼20 nm have been observed in scanning electron micrographs of the plated films. Still smaller features are observed in STM images of the exposed organosilane films.

A neural net approach to discrete Hartley and Fourier transforms

The authors present an electronic circuit, based on a neural (i.e. multiply connected) net to compute the discrete Fourier transform (DFT). They show both analytically and by simulation that the circuit is guaranteed to settle into the correct values within RC time constants (on the order of hundreds of nanoseconds), and they compare its performance to other on-chip DFT implementations. >

The Morphology of Electroless Ni Deposition on a Colloidal Pd(II) Catalyst

The surface morphology of a surface-bound colloidal Pd(II) catalyst and its effect on the particle sizes with the largest particles reaching approximately 50 nm in diameter. Catalyst surface coverages as low as 20% are found to be sufficient to initiate complete and homogeneous metallization. The distribution of particle sizes for the electroless metal deposit, found to be a function of plating time, is broad with the maximum Ni particle size exceeding 120 nm. Results indicate controlling the size of the bound catalyst is the principal determining factor in controlling the particle size of the electroless deposit. Modification of the surface by depleting the concentration of surface functional groups capable of binding catalyst is used to shift the size distribution of bound catalyst to smaller values. A resulting three-to fourfold reduction in the particle size of the electroless deposit is demonstrated.

A metal/oxide tunneling transistor

We have fabricated a nanometer-scale transistor that operates by using a gate field to modulate the transmission of electrons through a lateral metal/oxide tunnel barrier. Our initial devices have a 30-nm-wide lateral Nb/NbOx tunnel junction on top of a planar Al2O3/Al buried gate. We observe effective modulation of the source–drain current with gate bias at room temperature with negligible gate leakage current. We identify the materials issues that currently limit the device performance, and we offer direction for future device improvements.

Electron‐beam lithography with the scanning tunneling microscope

The scanning tunneling microscope (STM), operated in vacuum in the field emission mode, has been used in lithographic studies of the resist SAL‐601 from Shipley. Patterns have been written by raising the tip–sample voltage above −12 V while operating the STM in the constant current mode. Resist films, 50 nm thick, have been patterned and the pattern transferred into the GaAs substrate by reactive ion etching. The variation of feature size with applied dose and tip–sample bias voltage has been studied. Comparisons have been made to lithography with a 10 nm, 50 kV electron e‐beam in a JEOL JBX‐5DII in the same resist thickness films. In all cases the resist films were processed in the standard fashion before and after exposure. The STM can write smaller minimum features sizes and has a greater process latitude. Proximity effects are absent due to the reduced scattering range of the low energy primary electrons. However, the writing speed is slower, being limited by the response of the piezoelectric scanner....

Sub‐30 nm lithography in a negative electron beam resist with a vacuum scanning tunneling microscope

We report studies of minimum feature sizes in 50 nm films of the high‐resolution negative electron beam resist, SAL‐601‐ER7 from the Shipley Corporation. Developed linewidths of 27 nm and line spacing of 55 nm, from center to center, were produced by lithography with a vacuum scanning tunneling microscope (STM). In contrast, a minimum linewidth of 95 nm was obtained from exposure with a 17 nm (1/e diameter) 50 kV electron beam. Patterns written in the STM at electron energies down to 15 eV were visible in the developed resist. The limit at 15 eV is related to the operation of the STM and does not represent an exposure threshold energy for the resist.

Neutral networks for tactile perception

The real-time solution to a basic inverse problem of tactile perception is investigated. Regularized solutions of this problem are obtained by a neural-analog network. Favorable setting times and noise immunity are observed in simulations and breadboard level experiments.<<ETX>>

Fabrication of 15 nm wide trenches in Si by vacuum scanning tunneling microscope lithography of an organosilane self‐assembled film and reactive ion etching

Organosilane precursor molecules, here (aminoethylaminomethyl)phenethyltrimethoxysilane, or PEDA, are chemisorbed onto a Si surface forming a monolayer thick film. These films are patterned using the scanning tunneling microscope to locally modify the chemical reactivity and are then used as a template for selective electroless plating of a thin Ni film. Reactive ion etching in a C2F6/O2 mixture transfers this pattern into the substrate. Improvement over previous lithographic performance is achieved by growing the films on a passivated and lightly oxidized Si surface, optimizing the patterning conditions, and improving the metallization and etch chemistry. In this way, we have generated deep trenches on the order of 15±4 nm width, with edge roughness of 3 nm. We believe this demonstrates the resolution limiting factors of this lithographic process.

Low-voltage electron beam lithography with a scanning tunneling microscope

Studies of a polydiacetylene negative electron beam resist have been made in a scanning tunneling microscope operated in vacuum at pressures in the 10−8 Torr range. The resist can be imaged if it is applied as a thin film to a conductive flat substrate and the tip bias voltage is chosen appropriately. An exposure threshold energy close to 8 eV has been observed for the formation of raised features in the resist. A minimum feature size of about 20 nm has been measured when written at an energy just above the exposure threshold. Details of the necessary substrate preparation are described together with the operation of the scanning tunneling microscope during imaging and exposure. The exposure dose is applied by raising the bias voltage for a specific time while keeping the tip‐sample current constant which has permitted insights into the mechanisms of the resist exposure.

A metal/oxide tunnelling transistor

We have fabricated a new type of nanometre-scale transistor that operates by using a gate field to modulate the tunnelling probability of electrons through a lateral metal/oxide tunnel junction. Computer simulations predict that such a tunnelling transistor should have operating characteristics similar to those of a Si MOSFET but should be scalable to gate lengths. The device is composed entirely of noncrystalline materials, thus facilitating fabrication on a variety of substrates and multilayer stacking of devices for three-dimensional circuit architectures. Our initial devices have a 40 nm wide tunnel junction on top of a planar buried gate. Application of gate bias results in an order of magnitude modulation of the source-drain tunnelling current at 77 K. However, the device transconductance is smaller than predicted by modelling, which we attribute to the gate field not fully penetrating to the active region of the tunnel junction.