D. Park

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

PMOS body-tied FinFET (Omega MOSFET) characteristics

In this paper, we introduce PMOS body-tied FinFet characteristics. For this work, the 0.1/spl mu/m design ruled SRAM technology was used. I/sub D/-V/sub DS/ characteristics show that /spl Omega/ MOSFET apparently has lower DIBL characteristics than conventional PMOS transistor. On current of the /spl Omega/ MOSFET is higher than that of conventional device and can be improved by optimising unit processes.

A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique

A full FinFET DRAM core which consists of McFETs for both the sense amplifiers and the sub-word drivers, as well as FinFETs for the memory cell array has been developed. It will efficiently shrink chip size and improve chip performance, and therefore, meet requirements for the future DRAMs with 55nm or smaller design rule. Newly developed schemes which are a selective STT SiN liner removal process, a selective TiN gate stack and narrow active pitch patterning have been successfully integrated

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.

Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation voltage was achieved for the first time in low power application by the reduction of loading capacitance. Standby current was less than 15 /spl mu/A/chip. The highly manufacturable compact cell of 0.84 /spl mu/m/sup 2/ area was integrated using PR (photo resist) flow technology and novel contact layout.

1/2.5" 8 mega-pixel CMOS Image Sensor with enhanced image quality for DSC application

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed

Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology

As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was analyzed. The major source of leakage current on NMOS and PMOS devices was different pathways, and it was controlled by reduction of gate poly-Si oxidation thickness and the optimization of LDD implantation process. The load PMOS lifetime under the HEIP stress was over 10 years at 3.5V of operation voltage. The SNM margin was obtained in subthreshold operation region by increase the current of load transistor and compensated for the process variation. Finally, SRAM cell of 0.84 /spl mu/m/sup 2/ of size with 0.1 /spl mu/m design rule was successfully fabricated.