Jeffrey M. Calvert

Enabling Low-Temperature Bonding in Advanced Packaging Using Electrodeposited Indium

As the advancement of transistor nodes faces unprecedented challenges and work continues to extend Moores law at the back end of the line (BEOL), packaging has become one of the fastest growing segments in the semiconductor industry. Lead-free soldering is one of the most critical steps in interconnection at the packaging level. The evolution of packaging requirements for various devices is driving changes in lead-free solder material selection, with lower melting point being an emerging criterion. Indium, because of its unique properties such as high thermal and electrical conductivity, excellent ductility, and particularly the low melting point of 157 °C along with the capability of alloying with other metals (e.g. tin) to bring the melting point further down, is drawing increasing attention to its application in packaging, as a candidate for low temperature solders. In the current study, indium capping on standard and micro copper pillars was demonstrated. It was also shown that stacking indium and tin layers could form (near) eutectic indium-tin alloys after reflow with a melting point as low as 119 °C. The experimental next-generation indium electroplating chemistry demonstrated a strong potential to further improve the performance, such as a smoother surface morphology compared to the current generation chemistry, towards demanding requirements for future packaging applications.

From C4 to micro-bump: Adapting lead free solder electroplating processes to next-gen advanced packaging applications

SnAg solder is the industry standard for lead-free wafer bumping. SnAg electroplating chemistry for C4 bumping must be capable of achieving tight performance standards over a wide range of applications: mushroom or in-via electroplating, a diverse range of die designs and pattern densities, and over a wide range of plating rates, including high speeds to enable higher throughput. Beyond C4 applications, SnAg electroplating chemistries must also deliver strong performance on emerging micro-bumping and Cu pillar capping applications, leading to new materials challenges and new demands on both the solder and copper electroplating chemistries. Electrodeposited SnAg solder and Cu pillar performance is controlled by the specially formulated additives used during the electroplating process, paired with optimized high purity, low-alpha emitting inorganic metal salts and acids. Selection of robust, versatile SnAg and Cu plating chemistries capable of operation at high plating rate is critical to achieving optimized high volume, high throughput, and cost effective manufacturing. Improper additive selection can lead to a number of defects, which can manifest after plating, after reflow, or during reliability testing. These defects include as-plated defected or rough surface morphology, post-reflow macro-voiding, micro-voiding, bridging, and Ag3Sn plate formation, and poor height uniformity control across the die and wafer. These defects can lead to critical failures that lower yield and require wafer rework or wafer scrapping. To reduce the frequency of solder bumping, micro-bumping and Cu pillar capping defectivity, solder and Cu electroplating processes must be selected to enable wide process versatility and stability. In this paper, a wide range of bumping defects is introduced, root causes are discussed, and defect mitigation strategies are presented. Further, next-generation SnAg electroplating chemistries are presented that are designed to minimize solder defectivity and provide high performance, high yield, wide process windows, and high throughput options over a wide range of applications.