Christina Gimmler-Dumont

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Abstract The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.

A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers

Continued progressive downscaling of CMOS technologies threatens the reliability of chips for future embedded systems. We developed a novel design methodology for dependable wireless communication systems which exploits the mutual trade-offs of system performance, hardware reliability, and implementation complexity. Our cross-layer approach combines resilience techniques on hardware level with algorithmic techniques exploiting the available flexibility in the receiver. The overhead is minimized by recovering only from those hardware errors that have a strong impact on the system behavior. We apply our new methodology on a double-iterative MIMO-BICM receiver which belongs to the most complex systems in current communication standards.

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that manufacturing technology was responsible for ensuring device reliability. This basic assumption is no longer tenable. Trying to contain reliability problems purely at the technology level would cause prohibitive increases in power consumption. Thus, a cross-layer approach is required, which spreads the burden of ensuring resilience across multiple levels of the design hierarchy. This article illustrates a methodology for dealing with scaling-related problems via two case studies that link models of low-level technology-related problems to system behavior.

A system view on iterative MIMO detection: dynamic sphere detection versus fixed effort list detection

Multiple-antenna systems are a promising approach to increase the data rate of wireless communication systems. One efficient possibility is spatialmultiplexing of the transmitted symbols over several antennas. Many different MIMO detector algorithms exist for this spatialmultiplexing. The major difference between differentMIMOdetectors is the resulting communications performance and implementation complexity, respectively. Particularly closed-loop MIMO systems have attained a lot of attention in the last years. In a closed-loop system, reliability information is fed back fromthe channel decoder to the MIMO detector. In this paper, we derive a basic framework to compare different soft-input soft-output MIMO detectors in open- and closed-loop systems. Within this framework, we analyze a depth-first sphere detector and a breadth-first fixed effort detector for different application scenarios and their effects on area and energy efficiency on the whole system. We present all systemcomponents under open- and closed-loop system aspects and determine the overall implementation cost for changing an open-loop system in a closed-loop system.

Reliability study on system memories of an iterative MIMO-BICM system

Technology scaling leads to a decreasing reliability of the fabricated CMOS circuits. Designing reliable applications on unreliable circuitry is one of the big challenges of the next technology generations. Exploiting the knowledge of multiple abstraction layers from circuit and micro-architecture up to algorithm and application layer is key to minimizing dependability cost in terms of area, energy and performance. Fortunately, many applications dealing with imprecise information have an inherent error resilience. Therefore, it is mandatory to analyze the algorithmic error resilience of such applications and to find low-complexity protection methods. In this paper, we present the first study of the impact of hardware errors in the system memories of an iterative MIMO-BICM receiver. We classify the memories in different groups due to their robustness and compare resilience actuators on software, hardware and technology level to combat the hardware errors.

ASIC implementation of a modified QR decomposition for tree search based MIMO detection

Multiple-antenna systems offer very attractive gains in data rates and transmission reliability. Therefore, they are employed in many modern communication standards. However, the detection and separation of these multiple data streams can be very complex. For tree search based detection methods, a channel preprocessing is mandatory which consists mainly of a QR matrix decomposition. We propose a modification of the standard QR matrix decomposition which simplifies the tree search while not increasing the complexity of the QR decomposition. We present hardware architectures of the original and the modified QR decomposition. The resulting ASIC implementation in 65nm technology runs at a maximum clock frequency of 370 MHz and consumes an area of 0.14mm2. The power consumption at the specified clock frequency of 300 MHz is only 6.8mW.

A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems

Multiantenna telecommunication systems represent channels with multiple inputs and multiple outputs (MIMO) by matrices. QR decomposition (QRD) of the channel matrix is a crucial part of MIMO detection algorithms, such as successive interference cancellation or sphere detection. Modern standards like Long Term Evolution (LTE) require the processing of millions of matrices per second, in order to compensate channel changes that occur due to the mobility of the detector and Doppler spread. We introduce a new architecture for minimum mean square error (MMSE) sorted QR decomposition based on Givens rotations. The architecture is derived from classical systolic array approach but includes modifications to allow sorting and MMSE preprocessing. It balances throughput against area and fulfills the real-time requirements of 1.763 μs and 0.881 μs derived from the LTE MIMO standard when synthesized on ALTERA Stratix III and Stratix V family FPGAs. Moreover, it can trade speed for area and is suitable for tighter time constraints.

FPGA-based rapid prototyping platform for MIMO-BICM design space exploration

FPGA-based rapid-prototyping becomes more and more important for the design space exploration of wireless systems. FPGA-based platforms allow faster system exploration with a high degree of flexibility. In this paper, we present a rapid-prototyping platform for double-iterative MIMO-BICM systems which belong to the most complex communication systems of current and future (4G, 5G) standards. Unified streaming interfaces simplify the connection of system components and the replacement of individual components without influencing the rest of the system. Hardware verification is often a very time-consuming task. Therefore, the platform offers special testing features. To the best of our knowledge, this is the first hardware implementation of a double-iterative MIMO-BICM system including channel preprocessing, MIMO detection and channel decoding.