Christine Hu-Guo

First test results Of MIMOSA-26, a fast CMOS sensor with integrated zero suppression and digitized output

The MIMOSA pixel sensors developed in Strasbourg have demonstrated attractive features for the detection of charged particles in high energy physics. So far, full-size sensors have been prototyped only with analog readout, which limits the output rate to about 1000 frames/second. The new MIMOSA 26 sensor provides a 2.2 cm2 sensitive surface with an improved readout speed of 10,000 frames/second and data throughput compression. It incorporates pixel output discrimination for binary readout and zero suppression micro-circuits at the sensor periphery to stream only fired pixel out. The sensor is back from foundry since february 2009 and has being characterized in laboratory and in test beam. The temporal noise is measured around 13-14 e- and an operation point corresponding to an efficiency of 99.5±0.1 % for a fake rate of 10-4 per pixel can be reached at room temperature. MIMOSA 26 equips the final version of the EUDET beam telescope and prefigures the architecture of monolithic active pixel sensors (MAPS) for coming vertex detectors (STAR, CBM and ILC experiments) which have higher requirements. Developments in the architecture and technology of the sensors are ongoing and should allow to match the desired readout speed and radiation tolerance. Finally, the integration of MAPS into a micro-vertex detector is addressed. A prototype ladder equipped, on both sides, with a row of 6 MIMOSA 26-like sensors is under study, aiming for a total material budget about 0.3% X0.

Monolithic active pixel sensors with on-pixel amplification and double sampling operation

Abstract Monolithic Active Pixel Sensors (MAPS) constitute a novel technique for silicon position-sensitive detectors. Their development is driven by highly demanding performances of the vertex detector foreseen at the future linear collider. This paper presents a new approach for a detector based on the MAPS principle. The pixel concept proposed is foreseen to match with signal discrimination implemented on the chip. It combines on-pixel signal amplification with double sampling operation, and provides a signal resulting from the difference between the charges collected in two consecutive time slots. The device can be fabricated in a cheap standard CMOS process, using a wafer made of a moderately doped medium. The new pixel design uses only NMOS transistors, nwell/psub and pdiff/nwell diodes and poly1-to-poly2 capacitors. It is based on a principle of switched operation circuits with 15 transistor switches close to the minimum size and 14 transistors used for the signal amplification.

A reticle size CMOS pixel sensor dedicated to the STAR HFT

ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7 μm pixel pitch, providing a sensitive area of ~ 3.8 cm2. Based on the sensor designed for the EUDET beam telescope, the device is a binary output sensor with integrated zero suppression circuitry featuring a 320 Mbps data throughput capability. It was fabricated in a 0.35 μm OPTO process early in 2011. The design and preliminary test results, including charged particle detection performances measured at the CERN-SPS, are presented.

Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging

This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging

This paper presents design techniques of a multiphase clock generator using a low-jitter delay-locked loop (DLL) or its array for the developments of high-resolution multi-channel time-to-digital converters (TDCs). The low-jitter technologies for both a single DLL and an array of DLL are discussed. Based on the previous work on the design of a single DLL with 32 delay cells, an array of mixed-mode low-jitter DLLs is proposed for achieving smaller time taps. The array of DLL is successfully designed and embedded into a prototype chip of a three-channel high-resolution TDC in 0.35 CMOS process. The operational range of the DLL in the array is from 50 MHz to 120 MHz. The RMS value of measured cycle-to-cycle jitter in the DLL is about 7 ps while the peak-to-peak value is about 20 ps. A bin size of 71 ps can be achieved by using a reference clock of 100 MHz. The DNL and INL of the evaluated chip are 0.58 LSB and 0.63 LSB, respectively. The static power dissipation of the DLL array is about 23 mW.

Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp analog-to-digital converter (ADC) for a small animal positron emission tomography(PET) imaging system. The proposed ADC is a part of a monolithic front-end readout application-specific integrated circuit(ASIC) which is dedicated to the detector modules consisting of LYSO scintillation crystals read out on both sides by the multi-channel plate (MCP) photodetectors. The function of the ADC is to digitize the voltage signals from a large number of readout channels. Digital delay-locked loop (DLL) techniques are proposed to realize time interpolations in order to reduce the conversion time and to enhance the resolution. Both high precision and low power are obtained. An eight-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The available resolution of the ADC is 9 ~ 12 bits. The maximum DNL and INL of the fine conversion in the ADC is ±0.75 LSB and ±0.5 LSB, respectively. The static power consumption of the ADC is 3 mW + 0.2 mW/Channel. This ADC architecture provides a possibility to integrate low-noise front-end readout circuits, time-to-digital converters and ADC together into a monolithic ASIC and to output both the energy quantity and the time information with digital representations for PET imaging systems.

Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems

This paper presents a novel design of a 12-bit multi-channel single-ramp analog-to-digital converter (ADC) for imaging detector systems. To overcome the problem of long conversion time in the classic Wilkinson ADC, a new architecture using a counter and delay line interpolations is proposed. Two 5-bit Gray counters are designed for the coarse conversion. The time interpolation using an array of five delay-locked loops (DLLs) and the multiphase sampling technique are proposed for the fine conversion. The 140-phase delay clocks are generated by the array and pseudo 7-bit fine resolution is achieved. A one-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The total conversion time is about 400 ns, which corresponds to a sampling rate of 2.5 MS/s. The proposed ADC can be utilized in many fields, such as high-energy physics, biomedical imaging, and space applications.

Monolithic active pixel sensors with in-pixel double sampling operation and column-level discrimination

Monolithic Active Pixel Sensors constitute a viable alternative to Hybrid Pixel Sensors and Charge Coupled Devices for the next generation of vertex detectors. Possible application will strongly depend on a successful implementation of on-chip hit recognition and sparsification schemes. These are not a trivial task, first because of very small signal amplitudes (/spl sim/mV), originated from charge collection, which are of the same order as natural dispersions in a CMOS process, secondly because of the limitation to use only one type of transistor over the sensitive area. The paper presents a 30 /spl times/ 128 pixel prototype chip, featuring fast, column parallel signal processing. The pixel concept combines on-pixel amplification with double sampling operation. The pixel output is a differential current signal proportional to the difference between the charges collected in two consecutive time slots. The readout of the pixel is two-phase, matching signal discrimination circuitry implemented at the end of each column. The design of low-noise discriminators includes automatic compensation of offsets for individual pixels. The details of the chip design are presented. Difficulties, encountered from being the first attempt to address on-line hit recognition, are reported. Performances of the pixel and discriminator blocks, determined in separate measurements, are discussed. The essential part of the paper consists of results of first tests performed with soft X-rays from a /sup 55/Fe source.

Radiation tolerance of a column parallel CMOS sensor with high resistivity epitaxial layer

CMOS Monolithic Active Pixel Sensors (MAPS) demonstrate excellent performances in the field of charged particle tracking. A single point resolution of 1–2 μm and a detection efficiency close to 100% were routinely observed with various MAPS designs featuring up to 106 pixels on active areas as large as 4 cm2[1]. Those features make MAPS an interesting technology for vertex detectors in particle and heavy ion physics. In order to adapt the sensors to the high particle fluxes expected in this application, we designed a sensor with fast column parallel readout and partially depleted active volume. The latter feature was expected to increase the tolerance of the sensors to non-ionizing radiation by one order of magnitude with respect to the standard technology. This paper discusses the novel sensor and presents the results on its radiation tolerance.

Optimization of CMOS pixel sensors for high performance vertexing and tracking

Abstract CMOS Pixel Sensors tend to become relevant for a growing spectrum of charged particle detection instruments. This comes mainly from their high granularity and low material budget. However, several potential applications require a higher read-out speed and radiation tolerance than those achieved with the available devices based on a 0.35 μ m feature size technology. This paper shows preliminary test results of new prototype sensors manufactured in a 0.18 μ m process based on a high resistivity epitaxial layer of sizeable thickness. Grounded on these observed performances, we discuss a development strategy over the coming years to reach a full scale sensor matching the specifications of the upgraded version of the Inner Tracking System (ITS) of the ALICE experiment at CERN, for which a sensitive area of up to ∼ 10 m 2 may be equipped with pixel sensors.