Christophe Aumont

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

Electrical and morphological assessment of via middle and backside process technology for 3D integration

This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

3D integration demonstration of a wireless product with design partitioning

3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customers interest by showing him evaluations and results on real industrial applications. Heterogeneous integration and the possibility to partition different functions of a product in separate layers is one of the advantages of 3D integration. In this paper, product partitioning with TSV and 3D integration is demonstrated without inducing any impact on final product functionality and on early package level reliability tests.

WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation

Three-dimensional (3D) stacked IC technologies have become a central topic over the past few years, and start to become reality with the introduction of 3D devices in commercialization. Among the technical challenges raised by this technology, thin wafer handling remains one of the most challenging. A large number of publications have focused on this process since several years to present the performances of the different competitors. The goal of this paper is to discuss the 300mm interposer creation process using 2 of the most spread temporary bonding techniques: ZoneBOND™ and WSS (Wafer Support System). The comparison will be achieved during the different process steps considering 50μm or 80μm thick silicon interposers. The comparison will be done considering the 2 major challenges of temporary bonding integration: interposer flatness control and stability during the backside process. Finally this work has enabled us to identify the drawbacks and advantages of each technique for 3D integration.

Challenges and solutions for ultra-thin (50 μm) silicon using innovative ZoneBOND™ process

The purpose of this paper is to investigate integration results of 300mm silicon wafers thinned at 80μm down to 50μm using the innovative temporary ZoneBOND™ technology to handle the device during the process flow. A focus on the coating/bonding and thinning process of 80μm and 50μm thick silicon interposers is made. A tape selection study enabled us to identify two separation tapes compatible with varying interposer backside topology as well as the adhesive cleaning chemistries. After the validation of these fundamental processes, we created fully-functional interposers presenting 10×80 μm or 6Χ55μm TSVs. We measured the TTV and deformation through all the thinning and the backside processes. No significant TTV difference has been observed and all steps whatever the interposer type successfully pass the integration process. Finally, in order to increase the process window of the dielectric and TSV CMP, different oxide deposits are tested on 300mm temporary bondings thinned at 80μm or 50μm. This study confirmed that the dielectric deposition process remains one of the most challenging steps of the backside process. It has been observed that the use of hard mask type deposition process does not damage temporary bonding interface whereas TEOS type deposits at 200°C initiate damage at bonding edges which are more significant for 50μm interposer and thicker deposition layers. This work concludes on the process limitations with the use of ZoneBOND™ technology.

Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias

In this paper, we present an innovative solution to successfully metallize Through Silicon Vias (TSV) with High Aspect Ratio (10:1). These structures represent a key element in the 3D mid-process integration approach. The metallization consists in depositing, respectively, a diffusion barrier and a seed layer, using two different conformal deposition techniques. The technique used for the barrier material is based on a MOCVD TiN process while the second one involves a copper electrografting method. An additional copper Physical Vapor Deposition (PVD) layer is temporarily deposited to fulfill the requested properties and finalize a viable TSV integration on double sided 300mm design architecture. Further electrical characterizations of Kelvin TSVs and daisy chains are obtained. On a first hand, a 33mOhm resistance value is measured for a single 10×100μm via structure. This measurement is consistent with the theoretical value expected for this particular TSV design. On a second hand, contact continuity of up to 754 via chain structures validates the potential viability of this integration architecture for 3D device manufacturing.

Innovative Temperature and Heat Distribution Measurement Protocol Applied to 3D TSV Technology

This paper presents a new test protocol aimed at accurately determining the temperature of 3D electronic circuits as well as their heat distribution. It is based on AC electrical measurements coupled with InfraRed Lock-In Thermography (IR LIT) measurements. The circuit temperature is assessed thanks to AC resistance measurements and the Temperature Coefficient of Resistance (TCR) of metallic layers. The heat distribution is measured with an IR LIT system synchronized with the AC resistance measurement signal. The protocol has been applied on a Through Silicon Via (TSV) daisy chain of a silicon interposer on which temperature and heat distribution have been measured.

Photo-dielectric polymers material characterizations for 3D packaging applications

When considering wafer level packaging (WLP) applications, the use of dielectric polymer materials becomes more relevant for reliability performance. Indeed, polymer materials can have excellent dielectric performances with a processability at lower thermal balance. Their mechanical properties also offer a better compliance between the silicon 3D stack and the organic substrate underneath, improving the overall Front-End / Back End compatibility. This study reports the thermo-mechanical behavior and properties evaluation of the most advanced photo-sensitive dielectric polymers with higher resolution available in the market. It will allow direct comparisons between different dielectric polymer materials with the focus of stress control and thermal stability. First part of the paper will present thermal and mechanical characterization of these polymers performed with the same experimental conditions. Second part will present the advantages and limitations of each measurement characterization technique. And finally, the most relevant characterizations will be extracted in order to compare such dielectric polymers for 3D packaging applications.