Nicolas Hotellier

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

Electrical and morphological assessment of via middle and backside process technology for 3D integration

This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

3D integration demonstration of a wireless product with design partitioning

3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customers interest by showing him evaluations and results on real industrial applications. Heterogeneous integration and the possibility to partition different functions of a product in separate layers is one of the advantages of 3D integration. In this paper, product partitioning with TSV and 3D integration is demonstrated without inducing any impact on final product functionality and on early package level reliability tests.

Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.

Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments

Thermo-mechanical stresses have proven to be a critical issue in a typical interposer integration and assembly flow. However the nature of passive interposer makes the integration of MOS-based stress sensors impossible. New methods are required. Using a coupling strategy between 3D Finite Element Models (FEM) and physical characterization, a method based on electrical measurement of passive stress sensors is presented here to assess stress at die- and wafer-level. Innovative combination of passive stress sensors based on rosettes of serpentine resistors have been developed and embedded to quantify local strain states in a typical interposer die. Their principle and implementation at a copper interconnect level of interposer are presented in this paper. Preliminary results are depicted, including first electrical measurements of these sensors. Electrical characterization has been performed after the back-side interconnection fabrication of the interposer. A local sensibility of each copper serpentine is highlighted. Discrepancies in the resistance values of orthogonal resistors could indicate local deformations to the environment of sensors, such as TSVs and bump pads. However, the order of magnitude of relative variation of resistance values is unexpectedly high and requires further investigations.

Thermo-mechanical characterization of passive stress sensors in Si interposer

Passive stress sensors have been integrated in a silicon interposer test vehicle to investigate thermo-mechanical stress in a typical 2.5D system. The present sensors are integrated in a rosette-shape consisting of eight oriented copper serpentines acting like strain gauges. An innovative design allows theoretically the calculation of a partial stress tensor, including three planar and one out-of-plane components. Electrical measurements at wafer level, combined to FIB/SEM cross-sections, revealed a strong impact of elaboration processes on the structures electrical characteristics. Numerical simulations using finite element analysis were built to evaluated the theoretical sensitivity of copper serpentine to mechanical strains. Finally a dedicated four-point bending tool coupled with a four-terminal resistance measurement setup was fabricated to extract experimentally the values of sensors sensitivity factors. Preliminary results depicted in this paper highlight a sensitivity to stress of distinctly oriented resistors. Several identified sources of data dispersion are inherent to the present measurement configuration and prevent a reliable calculation of strain gauges so-called “gauge factors”.

Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors

One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTSs Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process ...