Christophe Verove

Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning

The present work focuses on the line width roughness (LWR) transfer and the critical dimension control during a typical gate stack patterning and shows the benefits of introducing 193 nm photoresist treatments before pattern transfer into the gate stack to improve process performance. The two investigated treatments (HBr plasma and vacuum ultra violet (VUV) plasma radiation) have been tested on both blanket photoresist films and resist patterns to highlight the etching and roughening mechanisms of cured resists. Both treatments reinforce the etch resistance of the photoresist exposed to fluorocarbon plasma etching process used to open the Si-ARC (silicon antireflective coating) layer. The etch resistance improvement of cured resists is attributed to both the decrease in oxygen content within the resist and the crosslinking phenomena caused by VUV radiation during the treatment. As the magnitude of the surface roughness is directly correlated to the etched thickness, cured resists, which are etched less rapidly, will develop a lower surface roughness for the same processing time compared to reference resists. The LWR evolution along the pattern sidewalls has been studied by critical dimension atomic force microscopy during the Si-ARC plasma etching step. The study shows that the LWR is degraded at the top of the resist pattern and propagates along the pattern sidewalls. However, as long as the degradation does not reach the interface between resist and Si-ARC, the LWR decreases during the Si-ARC etching step. As resist pretreatments reinforce the resist etch resistance during Si-ARC etching, the LWR degradation along the sidewalls is limited leading to minimized LWR transfer. The LWR decrease observed after plasma etching has been explained thanks to a spectral analysis of the LWR performed by critical dimension scanning electron microscopy combined with the power spectral density fitting method. The study shows that the high and medium frequency components of the roughness (periodicity below 200 nm) are not totally transferred during the gate patterning allowing a LWR decrease at each plasma step.

Integration of Fluorine-doped Silicon oxide in copper pilot line for 0.12-µm technology

The FSG (fluorine-doped silicon glass) was introduced as dielectric for copper interconnects in order to take advantage of its lower dielectric constant. With a gain of 18% in the constant value, it makes the shrink of metal dimension possible for 0.12- µm technology devices with limited cross-talks or delays in the information transmission. In spite of its strong sensitivity to water and moisture absorption, we could integrate this material in the dual damascene structure for copper application for 0.12- µm technology. The use of appropriate capping layer and optimisation of fluorine content made the integration possible with optimal dielectric properties.

Residue growth on metallic-hard mask after dielectric etching in fluorocarbon-based plasmas. I. Mechanisms

This work focuses on the formation of residues that grow on a metallic-hard mask after etching of porous low-k materials in fluorocarbon-based plasmas. The residue growth, which is dependent on the air exposure time after etching, causes line and via opens that strongly impact the yield performance. The different elements which could play a role in the chemical reactions have been clarified. The authors have demonstrated that in their experimental conditions, after fluorocarbon etching and air exposure, the oxidized titanium nitride reacts with fluorhydric acid to form metallic salts. This is a reaction between fluorine from the reactive layer formed on titanium nitride and hydrogen coming from the atmosphere. This reaction is all the more fast because the titanium nitride is oxidized.

Plasma treatments to improve line-width roughness during gate patterning

Abstract. The major issue related to line width roughness (LWR) is the significant LWR of the photoresist patterns printed by 193-nm lithography that is partially transferred into the gate stack during the subsequent plasma etching steps. The strategy used today to overcome this issue is to apply postlithography treatments to reduce photoresist pattern LWR before transfer. In this article, we investigate the impact of various plasma treatments (HBr, H2, He, Ar) on the minimization of the LWR of dense and isolated photoresist patterns and its transfer during gate patterning. To do so, we use critical dimension scanning electron microscopy measurements combined with power spectrum density fitting method to extract unbiased LWR values and provide a spectral analysis of the LWR. We show that plasma treatments that lead to carbon redeposition from the gas phase on the resist pattern sidewalls are less efficient to reduce LWR than plasma treatments where the redeposition is limited. Among all plasma chemistries, H2 plasmas seem very promising to decrease resist LWR in the whole spectral range, while maintaining square resist profiles. In addition, we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

Optimization of CVD dielectric process to achieve reliable ultra low-k air gaps

The capability of CVD silicon oxide has been studied to achieve a controlled air gap between copper interconnects for sub-quarter micron CMOS technologies. Several deposition parameters have been investigated and their influence on air gap morphology and electrical performances are shown in this paper. A reliable process has been obtained from these experiments. The parasitic capacitance between lines is reduced by half using SiO2 air gap material.

Plasma treatment to improve linewidth roughness during gate patterning

With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an accurate estimation of the CDSEM noise level and extraction of unbiased LWR. In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length, fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H2, He, Ar), and also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H2 that limit carbon redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

In situ post etching treatment as a solution to improve defect density for porous low-k integration using metallic hard masks

H2, O2, NH3 and CH4 in situ post-etching treatments (PET) have been investigated as a solution to prevent the residues formation (TiFx based) on TiN metallic hard mask (MHM) after etching in fluorocarbon based plasmas. The PET impact on the residues growth reduction on the mask and on the porous SiOCH modification is presented and discussed. The compatibility of the different PET is also evaluated for C045 dual damascene level using trench first MHM integration.

Scatterometric Porosimetry for porous low-k patterns characterization

Porous low-k dielectrics integration in interconnects is required to keep improving Integrated Circuits performance. However, these materials are highly sensitive to plasma processes and may be damaged during the patterning steps. Characterizing the plasma induced modification is required on patterned structures to develop less damaging plasma processes. Scatterometric Porosimetry (SP) has recently been introduced to characterize the plasma-induced porous low-k modification on patterned structures. By discussing the sensitivity and correlations of the different optimization parameters on a simple dielectric stack, we will show in which manner the SP method is applicable to fundamental studies and to process optimization.

Impact of ambient atmosphere on plasma-damaged porous low-k characterization

Improving Integrated Circuits performance requires the use of porous SiCOH in interconnects. However, porosity leads to plasma species diffusion into the material during the patterning steps, which damages the low-k properties. Characterizing plasma-damaged porous SiCOH is not straightforward, and requires a specific characterization setup and protocol. In this paper, we show the impact of the ambient atmosphere on the low-k properties, and how it should be taken into account during the characterization of plasma-damaged porous SiCOH.

Etching process scalability and challenges for ULK materials

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.