Christopher D. Hull

A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications

In recent years, there has been tremendous interest in trying to implement the power amplifier in CMOS, due to its cost and integration benefits. Most of the high power (watt-level) CMOS PAs reported to date have not exhibited sufficient linearity required for next generation wireless standards. In this paper, we report a single-chip linear CMOS PA with sufficient power and linearity for emerging OFDM-based 4G WiMAX applications. This 90 nm 2.4 GHz CMOS linear power amplifier uses a two-stage transformer-based power combiner and produces a saturated output power of 30.1 dBm with 33% PAE and 28 dB small-signal gain. A novel bypass network is introduced to ensure stability without sacrificing gain. The choice of optimal biasing and capacitive compensation produces very flat AM-AM and AM-PM response up to high power. The PA has been tested with OFDM modulated signal and produces EVM better than -25 dB at 22.7 dBm average power. Graceful power back-off is demonstrated through turning off one of the stages, allowing low-power operation with enhanced efficiency.

A single-chip highly linear 2.4GHz 30dBm power amplifier in 90nm CMOS

In recent years, there has been tremendous interest in trying to implement power amplifiers (PAs) in CMOS, due to cost and integration benefits. However, the low supply voltage, conductive substrate, and high loss of on-chip passives make monolithic, linear, high-power PA design challenging in CMOS. Most of the high-power CMOS PAs reported to date are switching-type [1,2], and have not exhibited sufficient linearity required for modern wireless standards. In this paper, a single-chip linear CMOS PA with sufficient power and linearity for emerging OFDM-based applications is reported. This 90nm fully-integrated PA adopts a differential topology and operates at 3.3V supply.

A 90nm CMOS power amplifier for 802.16e (WiMAX) applications

We demonstrate a single stage 90nm CMOS power amplifier for 2.3−2.7GHz WiMAX (802.16e) band applications. An integrated BALUN is used to match the output to 50ohm load. The PA gain and saturated power are +18dB and +32dBm, respectively, working from a 3.3V supply, with a peak power added efficiency (PAE) of 48%. Digital pre distortion (DPD) technique is used to enhance the PA linearity. The measured EVM for a 64-QAM OFDM signal is improved from −24dB to −30dB at +25dBm output power. Compliance with the FCC 10MHz WiMAX mask is demonstrated at +25dBm of output power with power efficiency of ∼25%. Under these conditions, the measured second harmonic level at the PA output is −31[dBm/MHz].

A 60 GHz Drain-Source Neutralized Wideband Linear Power Amplifier in 28 nm CMOS

CMOS technology scaling has enabled the design of high speed and efficient digital circuits. However, the continued scaling is detrimental to the design of RF and mm-wave systems. Higher sensitivity to process variations and inaccuracies in modeling of active and passive devices pose another challenge to the design of these systems at deep submicron technology nodes. This paper describes the design of a 60 GHz power amplifier in 28 nm CMOS technology. A drain-source neutralization technique maintains the stability of the PA and the wideband nature is achieved by the application of low-k transformer networks. The PA comprises of three stages and achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB. Using a two-way transmission line based power combiner, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%.

A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS

The rapid scaling of CMOS technology in the last decade has enabled the design of high speed and efficient digital CMOS circuits. However, the design of RF and mm-wave systems has become more challenging due to inaccuracies in modeling and increased losses in the active and passive devices. This paper presents the design of a 60 GHz linear wideband power amplifier (PA) in deeply scaled 28 nm CMOS technology. The PA utilizes cascode drain-source neutralization to improve stability and low-k transformer techniques to achieve high bandwidth. Using transmission line power combining, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%. The three stage PA achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB.

A Transformer-Based Broadband Front-End Combo in Standard CMOS

This paper presents a broad band front-end combo scheme based on a three-way on-chip transformer. The combo scheme functions as the T/R switch, balun, and impedance matching network simultaneously. A design example implemented in a standard 90 nm CMOS process demonstrates a 2 GHz 1-dB bandwidth from 5 GHz to 7 GHz. During the transmitting (TX) mode, the reported design achieves 2.65 dB insertion loss, +45.7 dBm IIP3, and 42 dB antenna-to-receiver isolation; in the receiving (RX) mode, the design demonstrates 2.52 dB insertion loss, +44.2 dBm IIP3, and 42 dB antenna-to-transmitter isolation. The TX-to-RX isolation is kept below 50 dB. The front-end combo design occupies a compact core area of 0.5 mm2 which includes the on-chip transformer.

An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration

A mixer-first receiver design in 28-nm CMOS is discussed. An embedded 5-bit mixer digital-to-analog converter provides wideband tuneability to enhance device matching and, hence, suppress the multiple local oscillator (LO) harmonics as well as to improve the overall image rejection (IR) performance. Two-stage baseband amplifiers support a 50-MHz baseband bandwidth, which covers the entire channel for long-term evolution non-contiguous carrier aggregation. The proposed design effectively reduce multiple LO harmonics down to below -62 dBm. The system achieves 2.6-dB noise figure, > 15-dBm out-of-band third-order input intercept point, and an IR ratio > 66 dB with 60-mW power, including five on-chip low dropout regulators.

A circuit designer's guide to 5G mm-wave

The fourth generation mobile phone standards (4G) in widespread use include Long Term Evolution (LTE) and LTE-A (Advanced), which support up to 44 bands internationally, or an aggregate bandwidth of about 1 GHz in TDD and FDD modes. Techniques such as carrier aggregation allow the mobile operator to maximize bandwidth and deliver high data rate to users. As demand for wireless connectivity continues to grow exponentially, a fifth generation (5G) standard is envisioned, with the requirement to deliver higher throughputs, more spectrum-particularly in the mm-wave bands-higher capacity through spatial diversity, and lower latency. The projected deployment date of 5G is in 2019, and various proposals are under consideration. This paper will highlight important implications for the design of transceivers for 5G, particularly those targeting the mm-wave bands.

Overlapped inductors and its application on a shared RF front-end in a MultiStandard IC

A technique to build overlapped inductors at the same location while keeping good isolation between them is presented. The key idea is to use magnetic and electric cancellation to reduce coupling. A shared LNA for WiFi and Bluetooth (BT) applications using the overlapped inductor is proposed. It enables independent gain control up to the first RF stage in a receiver so that the system integration complexity is reduced.

A passive-mixer-first receiver with LO leakage suppression, 2.6dB NF, >15dBm wide-band IIP3, 66dB IRR supporting non-contiguous carrier aggregation

A passive-mixer-first receiver design in 28 nm CMOS is presented where the front-end 5-bit mixer DAC provides a wide-band tuneable impedance match to suppress the LO leakage as well as to improve image rejection performance. Baseband LNA together with the AC-boosting compensation amplifier provides a 50MHz baseband bandwidth, which allows support for non-contiguous carrier aggregation for LTE. The proposed design can suppress multiple LO harmonics down below -62dBm. The system achieves <; 3dB NF, >15dBm IIP3 and an IRR > 66dB with 60mW power.