Stefano Pellerano

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for ldquocorrect-by-constructionrdquo design at mm-wave frequencies and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with a NF of 6.5 dB, while drawing 26mA per stage from 1.65 V. Output is 3.8 dBm. At , each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB, respectively. Measured results are in excellent agreement with simulations, proving the effectiveness of the proposed design methodology. A custom set-up for mm-wave NF measurement is also extensively described in the paper.

A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS

A mm-wave power-harvesting RFID tag is implemented in 90 nm CMOS. Operation at mm-wave reduces antenna size and could allow antenna integration on-chip. This, together with power harvesting that can be used in lieu of a battery, can result in a pinless, CMOS-only tag with no package and no off-chip components whatsoever. The tag harvests energy from the incoming mm-wave continuous wave (CW) signal transmitted by the reader and then uses a 60 GHz free-running oscillator to transmit back pulse-width modulated bursts. An in-depth treatment of the voltage multiplier and associated matching network and implications on tag range are presented. With 2 dBm mm-wave input power, the tag achieves a rate of 5 kb/s. The RFIC size is 1.3 × 0.95 mm2 including pads.

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a resolution of 1.4 ps (8 bit) required to meet WiFi requirements. A phase MUX architecture is proposed to implement switching between phases once every LO period (2.4 GHz) without generating detrimental glitches at the output. Due to its open-loop nature, the proposed phase modulator is capable of delivering wide OFDM bandwidths up to 40 MHz. The paper analyzes the impact of impairments, e.g., delay mismatch within the delay cells and outphasing mismatches, as well as associated mitigation techniques. The transmitter has been implemented in a 32-nm digital CMOS process and delivers an OFDM average power of 20 dBm with an overall system efficiency of 18.6% when transmitting 54-Mb/s 64QAM signal. The fully digital design is expected to further improve in power dissipation and chip-area with further CMOS scaling.

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS

This paper presents a fractional frequency divider-by-1.25 and associated all-digital calibration circuitry. The divider can be used in a wireless transceiver to prevent direct or harmonic pulling of the VCO by the power amplifier. Timing errors between the quadrature phases used in the phase-rotating divider introduce fractional spurs at the output. In this design, the timing errors are measured with a stochastic time-to-digital converter with 20 fs resolution, and corrected to suppress output spurs. The fractional divider has been implemented in a 45 nm CMOS LP process and its core dissipates an estimated 17 mA current from a 1.1 V supply. After calibration, fractional spurs are on average below -59 dBc and -50 dBc (¿ ~ 2 dB over 10 samples) with a 2.5 and 3.8 GHz output frequency respectively. Calibration performance has been confirmed for temperatures from -20°C up to 85°C. The low spur level facilitates radio co-existence with no need for additional filtering. This makes this divider a good candidate for WiFi and WiMAX radios up to 3.8 GHz.

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

In this paper, we present a 39.1-to-41.6 GHz 1.2 V 64 mW DeltaSigma fractional-N frequency synthesizer that is implemented in 90nm CMOS. To reduce power consumption, a divide-by-4 injection-locking frequency divider (ILFD) is used in the feedback loop and a digital calibration technique is implemented to overcome the ILFD locking-range limitations.

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS

Integration of radios in SoCs along with digital baseband and application processors is desirable for cost and form-factor reasons. Digital processors are typically implemented in the latest CMOS process to take advantage of the increased density and performance afforded by CMOS scaling. Integration of traditional RF circuits, however, requires accurate RF and passive models that typically lag behind digital transistor models by several quarters. This makes RF integration the limiting factor for time-to-market for the whole SoC, or results in sub-optimal multiple-chip solutions. Furthermore, traditional RF circuits do not benefit from scaling as digital circuits do, e.g. due to extensive use of inductors, the ever-lowering supply voltage, etc. This work presents a digital WiFi transmitter (TX) implemented in a 32nm digital CMOS process to address these issues. An outphasing architecture allows implementation of both amplitude and phase modulation using scaling-friendly, delay-based, switching phase modulators. The integrated PA was already shown to be possible to design with no RF models [1]; known issues of outphasing PA design (e.g. output impedance modulation, linearity, efficiency) are also addressed in [1]. The phase modulator uses an open-loop architecture to accommodate OFDM bandwidths up to 40MHz. The TX achieves state-of-the-art performance already in 32nm and is moreover expected to: (1) improve with scaling and (2) port easily over successive process nodes.

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management

A VCO used in a PLL inside a wireless transceiver can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency (fVCO) with respect to the PA. Multistandard radios covering, for example, WiFi 2.4 to 2.5GHz and 5 to 5.8GHz, and WiMAX 2.3 to 2.7GHz and 3.3 to 3.8GHz, may require multiple VCOs and/or multiple fractional dividers to cover all bands [1], resulting in complexity and area overhead. This paper proposes a versatile reconfigurable fractional divider capable of covering the above standards with a single VCO with 20% tuning range. The divider is all-digital, hence scaling-friendly, and uses digital calibration to eliminate the need for filtering and area-intensive inductors. The versatility afforded by the reconfigurable fractional divider allows for the transceivers LO generation (LOG) frequency plan to be adjusted on-the-fly. This can avoid VCO pulling from interferers which may not be known a-priori, like SoC-CPU clocks that are adjusted dynamically for best performance.

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

Increasing channel capacity on MIMO system employing adaptive pattern/polarization reconfigurable antenna

This paper presents a pattern/polarization reconfigurable single turn square spiral microstrip antenna that is designed to operate in the 5 GHz indoor band and tested with Intel-developed CMOS MIMO transceivers. Experimental results show that different environments between transmitter and receiver antenna MIMO system require different antenna configurations to achieve lower correlation between paths and increase the throughput.