Christopher Heidelberger

Remote epitaxy through graphene enables two-dimensional material-based layer transfer

Epitaxy—the growth of a crystalline material on a substrate—is crucial for the semiconductor industry, but is often limited by the need for lattice matching between the two material systems. This strict requirement is relaxed for van der Waals epitaxy, in which epitaxy on layered or two-dimensional (2D) materials is mediated by weak van der Waals interactions, and which also allows facile layer release from 2D surfaces. It has been thought that 2D materials are the only seed layers for van der Waals epitaxy. However, the substrates below 2D materials may still interact with the layers grown during epitaxy (epilayers), as in the case of the so-called wetting transparency documented for graphene. Here we show that the weak van der Waals potential of graphene cannot completely screen the stronger potential field of many substrates, which enables epitaxial growth to occur despite its presence. We use density functional theory calculations to establish that adatoms will experience remote epitaxial registry with a substrate through a substrate–epilayer gap of up to nine ångströms; this gap can accommodate a monolayer of graphene. We confirm the predictions with homoepitaxial growth of GaAs(001) on GaAs(001) substrates through monolayer graphene, and show that the approach is also applicable to InP and GaP. The grown single-crystalline films are rapidly released from the graphene-coated substrate and perform as well as conventionally prepared films when incorporated in light-emitting devices. This technique enables any type of semiconductor film to be copied from underlying substrates through 2D materials, and then the resultant epilayer to be rapidly released and transferred to a substrate of interest. This process is particularly attractive in the context of non-silicon electronics and photonics, where the ability to re-use the graphene-coated substrates allows savings on the high cost of non-silicon substrates.

Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach

Vertical In0.53Ga0.47As Gate-all around (GAA) nanowire (NW) MOSFETs fabricated by a top-down approach are demonstrated experimentally for the first time. The fabrication process features a new III-V dry etch process capable of sub-20 nm diameter NWs with an aspect ratio greater than 10. It also includes a digital etch technique to controllably reduce nanowire diameter and remove dry etch damage. With a channel length Lch=80 nm and EOT=2.2 nm, we obtain a transconductance of 730 μS/μm at 0.5 V in a 50 nm diameter NW MOSFET. The digital etch increases the transconductance by 20% and improves the subthreshold characteristics of the devices. In terms of balance of transport and short-channel effects, our MOSFETs match the best vertical nanowire devices fabricated by bottom-up techniques.

Heteroepitaxial growth of In0.30Ga0.70As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

We report on the growth of an In0.30Ga0.70As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 107 cm−2 with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with IDS of 70 μA/μm and gm of above 60 μS/μm, demonstrating the high quality of the grown materials.

Improved retention of phosphorus donors in germanium using a non-amorphizing fluorine co-implantation technique

Co-doping with fluorine is a potentially promising method for defect passivation to increase the donor electrical activation in highly doped n-type germanium. However, regular high dose donor-fluorine co-implants, followed by conventional thermal treatment of the germanium, typically result in a dramatic loss of the fluorine, as a result of the extremely large diffusivity at elevated temperatures, partly mediated by the solid phase epitaxial regrowth. To circumvent this problem, we propose and experimentally demonstrate two non-amorphizing co-implantation methods; one involving consecutive, low dose fluorine implants, intertwined with rapid thermal annealing and the second, involving heating of the target wafer during implantation. Our study confirms that the fluorine solubility in germanium is defect-mediated and we reveal the extent to which both of these strategies can be effective in retaining large fractions of both the implanted fluorine and, critically, phosphorus donors.

GaAsP/InGaP heterojunction bipolar transistors grown by MOCVD

Heterojunction bipolar transistors with GaAsxP1−x bases and collectors and InyGa1−yP emitters were grown on GaAs substrates via metalorganic chemical vapor deposition, fabricated using conventional techniques, and electrically tested. Four different GaAsxP1−x compositions were used, ranging from x = 0.825 to x = 1 (GaAs), while the InyGa1−yP composition was adjusted to remain lattice-matched to the GaAsP. DC gain close to or exceeding 100 is measured for 60 μm diameter devices of all compositions. Physical mechanisms governing base current and therefore current gain are investigated. The collector current is determined not to be affected by the barrier caused by the conduction band offset between the InGaP emitter and GaAsP base. While the collector current for the GaAs/InGaP devices is well-predicted by diffusion of electrons across the quasi-neutral base, the collector current of the GaAsP/InGaP devices exceeds this estimate by an order of magnitude. This results in higher transconductance for GaAsP/InG...

GaAsP/InGaP HBTs grown epitaxially on Si substrates: Effect of dislocation density on DC current gain

Heterojunction bipolar transistors (HBTs) with GaAs0.825P0.175 bases and collectors and In0.40Ga0.60P emitters were integrated monolithically onto Si substrates. The HBT structures were grown epitaxially on Si via metalorganic chemical vapor deposition, using SiGe compositionally graded buffers to accommodate the lattice mismatch while maintaining threading dislocation density at an acceptable level (∼3 × 106 cm−2). GaAs0.825P0.175 is used as an active material instead of GaAs because of its higher bandgap (increased breakdown voltage) and closer lattice constant to Si. Misfit dislocation density in the active device layers, measured by electron-beam-induced current, was reduced by making iterative changes to the epitaxial structure. This optimized process culminated in a GaAs0.825P0.175/In0.40Ga0.60P HBT grown on Si with a DC current gain of 156. By considering the various GaAsP/InGaP HBTs grown on Si substrates alongside several control devices grown on GaAs substrates, a wide range of threading disloca...

Source/Drain Asymmetry in InGaAs Vertical Nanowire MOSFETs

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work.

Defect and temperature dependence of tunneling in InGaAs/GaAsSb heterojunctions with varying band alignments

Summary form only given. In this work, we utilize two-terminal measurements of conductance slope as a means to probe the nature of tunneling at the interface without convolution of three-terminal parasitic effects such as gate-oxide traps or parasitic leakage pathways resulting from the more complicated geometry of a three-terminal device. The conductance slope gives an approximation to a transistor response in two terminals. [6,7] By removing three-terminal parasitics, the true nature of tunneling and its dependence on materials defects can be seen. Additionally, it allows for a comparison to be made between tunneling with and without gate-oxide traps present to better determine if such defects could be playing a role in the observed temperature dependence of published devices. In this work, we epitaxially grow InAs/GaSb and InGaAs/GaAsSb of varying alloying compositions and hence, varying band alignments. We study the effect of material defects on conductance slope at different band alignments via the effect of buffer layers to grade the strain. We also examine the temperature dependence of conductance slope to make important insights into the true nature of tunneling at the interface in the absence of oxide traps.