Christopher L. Henderson

THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS

The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.

IC failure analysis: magic, mystery, and science

Advancing IC and packaging technologies motivate and direct the future of failure analysis. The authors review current tools and techniques and discuss challenges and opportunities created by the industrys critical need for new diagnosis and failure analysis paradigms.

Signature analysis for IC diagnosis and failure analysis

A method of signature analysis is presented that is based on ATE data, experiential knowledge of failure modes and mechanisms, or a combination of both. This method can be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. This method can be used for rapid diagnosis of complex IC failures. The model is developed and an example is given based on Sandias 0.5 /spl mu/m CMOS IC technology.

IC failure analysis tools and techniques-magic, mystery, and science

This review includes a discussion of the advances being made to meet the challenges presented by state-of-the-art IC and packaging technologies, since these provide the motivation and direction for the future of FA. New capabilities are required for ICs with features such as additional interconnection layers, power distribution planes, or flip chip packaging that reduce or prevent the use of conventional methods without destructive deprocessing. To support improved time to market and yield enhancement, the industry needs diagnostic techniques that provide logical and physical localization in real time during production testing.

Economic Impact of Type I Test Errors at System and Board Levels

The economic impact of Type I test errors that fail good product in electronic systems and PC boards is evaluated. Data show that an average of 46 percent of all valid component failures at the board and system level are, in fact, not failures. Data are given in several formats and a model is presented showing the impact on quality of bonepile testing. A model that predicts the impact on quality of bonepile testing is presented. This model is used to predict quality impact for three different cases. The data also show that accurate diagnostic techniques should be designed into the product.

ICFAX, an integrated circuit failure analysis expert system

An expert system to aid in the analysis of failed integrated circuits has been developed. The integrated circuit failure analysis expert system (ICFAX) captures a substantial portion of the procedural knowledge necessary to successfully analyze CMOS integrated circuit failures. ICFAX is designed to apply generically to all types of CMOS ICs. ICFAX also contains general information on how to analyze components as well as product specific information, including schematics, layout plots, product specifications, and fabrication data. The expert system centralizes textual and graphical knowledge about failure analysis, increasing the analysts productivity and ability to determine the failure.<<ETX>>

The advent of failure analysis software technology

The increasing complexity of integrated circuits demands that software tools, in addition to hardware tools, be used for successful diagnosis of failure. A series of customizable software tools have been developed that organize failure analysis information and provide expert level help to failure analysts to increase their productivity and success.<<ETX>>

Challenges for IC failure analysis-present and future

Failure analysis is a critical element in integrated circuit manufacturing. This paper explores the challenges for IC failure analysis in the environment of present and future silicon IC technology trends, using the 1994 National Technology Roadmap for Semiconductors as a technology guide. Advanced techniques that meet the challenges of state-of-the-art IC technology are described and their applications are discussed. New approaches shall be required for failure analysis to keep pace with future advancements in IC technology.

IC diagnosis: industry issues

A new failure analysis paradigm is necessary-a shift from hardware-based techniques to software-based methods. The transition is a daunting task because of its complexity. As with other successful practices in microelectronics, including design and testing, it is expected that a suite of software applications will be necessary to thoroughly diagnose complex ICs. These tools should be able to run concurrent with or independent of production testing. When running concurrent with testing, they should be able to provide at least a pareto distribution of the dominant failure modes and mechanisms. Approaches include electrical behavior description using defect classes and high level heuristics compatible with VHDL design tools. It is critical that those working in IC design and test understand the rapidly increasing need for software diagnosis tools and support their development for the semiconductor industry.