Edward I. Cole

Resistive interconnection localization

Resistive interconnection localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients in IC interconnections during functional testing. A change in the pass/fail state with localized heating of the IC identifies the failing site. The technique reduces the time to locate a resistive via from months to minutes. The sources of defective vias, the physics of RIL signal generation, and examples of RIL analysis are presented.

TIVA and SEI developments for enhanced front and backside interconnection failure analysis

Thermally-Induced Voltage Alteration (TIVA) and Seebeck Effect Imaging (SEI) are newly developed techniques for localizing shorted and open conductors from the front and backside of an IC. Recent improvements have greatly increased the sensitivity of the TIVA/SEI system, reduced the acquisition times by more than 20X, and localized previously unobserved defects. The system improvements, non-linear response of IC defects to heating, modeling of laser heating and examples using the improved system are presented.

Electrostatic discharge/electrical overstress susceptibility in MEMS: a new failure mode

Electrostatic discharge (ESD) and electrical overstress (EOS) damage of Micro-Electrical-Mechanical Systems (MEMS) has been identified as a new failure mode. This failure mode has not been previously recognized or addressed primarily due to the mechanical nature and functionality of these systems, as well as the physical failure signature that resembles stiction. Because many MEMS devices function by electrostatic actuation, the possibility of these devices not only being susceptible to ESD or EOS damage but also having a high probability of suffering catastrophic failure doe to ESD or EOS is very real. Results from previous experiments have shown stationary comb fingers adhered to the ground plane on MEMS devices tested in shock, vibration, and benign environments [1,2]. Using Sandia polysilicon microengines, we have conducted tests to establish and explain the EDS/EOS failure mechanism of MEMS devices. These devices were electronically and optically inspected prior to and after ESD and EOS testing. This paper will address the issues surrounding MEMS susceptibility to ESD and EOS damage as well as describe the experimental method and results found from EDS and EOS testing. The tests were conducting using conventional IC failure analysis and reliability assessment characterization tools. In this paper we will also present a thermal model to accurately depict the heat exchange between an electrostatic comb finger and the ground plane during an ESD event.

Rapid localization of IC open conductors using charge-induced voltage alteration (CIVA)

Charge-induced voltage alteration (CIVA) is a new scanning electron microscopy technique developed to localize open conductors, on both passivated and depassivated ICs. CIVA overcomes the limitations usually encountered in localizing open conductors. CIVA images are produced by monitoring the voltage fluctuations of a constant current power, supply as an electron beam is scanned over the IC surface. Contrast variations in the CIVA images are generated only from the electrically open portion of a conductor. Because of this high selectivity, CIVA facilitates localization of open interconnections on an entire IC in a single, unprocessed image. The equipment needed to implement CIVA and examples of applying the technique to several failed CMOS ICs are described. Possible irradiation effects and methods to minimize them are also discussed.<<ETX>>

FLIP-chip and “backside” techniques

State-of-the-art techniques for failure localization and design modification through bulk silicon are essential for multi-level metallization and new, flip chip packaging methods. The tutorial reviews the transmission of light through silicon, sample preparation, and backside defect localization techniques that are both currently available and under development. The techniques covered include emission microscopy, scanning laser microscope based techniques (electrooptic techniques, LIVA and its derivatives), and other non-IR based tools (FIB, e-beam techniques, etc.).

Soft defect localization (SDL) in integrated circuits using laser scanning microscopy

Soft defects in integrated circuits (ICs) are defined as failures when the IC is partially functional, but will not operate properly under all specified conditions - these conditions may be within or outside normal limits. To address soft defects, a laser scanning methodology termed soft defect localization (SDL) was developed that rapidly locates soft defects in integrated circuits. The SDL method evaluates the pass/fail state of a device in response to localized laser heating to successfully localize soft defects. The method operates globally by scanning the laser over the entire die to quickly isolate soft defects in a matter of minutes. The SDL imaging system and methodology will be described followed by the presentation of several examples.

Internal current probing of integrated circuits using magnetic force microscopy

A model for the magnetic force microscopy (MFM) imaging of IC currents is presented. MFM signal generation is described and the ability to analyze current direction and magnitude with a sensitivity of approximately 1 mA DC and approximately 1 mu A AC is demonstrated. Experimental results are a significant improvement over the 100 mA AC resolution previously reported using an electron beam to detect IC currents.<<ETX>>

Magnetic force microscopy/current contrast imaging: a new technique for internal current probing of ICs

Abstract This invited paper describes recently reported work on the application of magnetic force microscopy (MFM) to image currents in IC conductors [1]. A computer model for MFM imaging of IC currents and experimental results demonstrating the ability to determine current direction and magnitude with a resolution of ∽ 1 mA dc and ∽ 1 μA ac are presented. The physics of MFM signal generation and applications to current imaging and measurement are described.

Failure analysis of radio frequency (rf) micro-electro-mechanical systems (MEMS)

MEMS are rapidly emerging as critical components in the telecommunications industry. This enabling technology is currently being implemented in a variety of product and engineering applications. MEMS are currently being used as optical switches to reroute light, tunable filters, and mechanical resonators. Radio frequency (RF) MEMS must be compatible with current Gallium Arsenide (GaAs) microwave integrated circuit (MMIC) processing technologies for maximum integration levels. The RF MEMS switch discussed in this paper was fabricated using various layers of polyimide, silicon oxynitride (SiON), gold, and aluminum monolithically fabricated on a GaAs substrate. Fig. 1 shows a metal contacting series switch. This switch consists of gold signal lines (transmission lines), and contact metallization. SiON was deposited to form the fixed-fixed beam, and aluminum was deposited to form the top actuation electrode. To ensure product performance and reliability, RF MEMS switches are tested at both the wafer and package levels. Various processing irregularities may pass the visual inspection but fail electrical testing. This paper will focus on the failure mechanisms found in the first generation of RF MEMS developed at Sandia National Laboratories. Various tools and techniques such as scanning electron microscopy (SEM), resistive contrast imaging (RCI), focused ion beam (FIB), and thermally-induced voltage alteration (TIVA) have been employed to diagnose the failure mechanisms. The analysis performed using these tools and techniques led to corrective actions implemented in the next generation of RF MEMS metal contacting series switches.

Electron and optical beam testing of integrated circuits using CIVA, LIVA, and LECIVA

Charge-Induced Voltage Alteration (CIVA), Light-Induced Voltage Alteration, (LIVA), and Low Energy CIVA (LECIVA) are three new failure analysis imaging techniques developed to quickly localize defects on ICs. All three techniques utilize the voltage fluctuations of a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA yield rapid localization of open interconnections on ICs. LIVA allows quick localization of open-circuited and damaged semiconductor junctions. LIVA can also be used to image transistor logic states and can be performed from the backside of ICs with an infrared laser source. The physics of signal generation for each technique and examples of their use in failure analysis are described.