Richard E. Anderson

IC failure analysis: techniques and tools for quality reliability improvement

The role of failure analysis is discussed. Failure analysis techniques and tools, including electrical measurements, optical microscopy, thermal imaging analysis, electron beam techniques, light emission microscopy, ion beam techniques, and scanning probe microscopy, are reviewed. Opportunities for advances in the field of IC failure analysis are considered. >

Electrostatic discharge/electrical overstress susceptibility in MEMS: a new failure mode

Electrostatic discharge (ESD) and electrical overstress (EOS) damage of Micro-Electrical-Mechanical Systems (MEMS) has been identified as a new failure mode. This failure mode has not been previously recognized or addressed primarily due to the mechanical nature and functionality of these systems, as well as the physical failure signature that resembles stiction. Because many MEMS devices function by electrostatic actuation, the possibility of these devices not only being susceptible to ESD or EOS damage but also having a high probability of suffering catastrophic failure doe to ESD or EOS is very real. Results from previous experiments have shown stationary comb fingers adhered to the ground plane on MEMS devices tested in shock, vibration, and benign environments [1,2]. Using Sandia polysilicon microengines, we have conducted tests to establish and explain the EDS/EOS failure mechanism of MEMS devices. These devices were electronically and optically inspected prior to and after ESD and EOS testing. This paper will address the issues surrounding MEMS susceptibility to ESD and EOS damage as well as describe the experimental method and results found from EDS and EOS testing. The tests were conducting using conventional IC failure analysis and reliability assessment characterization tools. In this paper we will also present a thermal model to accurately depict the heat exchange between an electrostatic comb finger and the ground plane during an ESD event.

Radiation hard 1.0μm CMOS technology

This paper describes radiation test results of a radiation hard CMOS technology with 1.0 μm minimum geometry features. The radiation goals of this technology are to ensure the MOS devices are functional after 10 Mrad total dose irradiation, are single event upset hardened to less than 1E-10 errors per bit-day, are transient upset immune to 1E9 rads/sec and are latch-up free.

IC failure analysis: magic, mystery, and science

Advancing IC and packaging technologies motivate and direct the future of failure analysis. The authors review current tools and techniques and discuss challenges and opportunities created by the industrys critical need for new diagnosis and failure analysis paradigms.

Rapid localization of IC open conductors using charge-induced voltage alteration (CIVA)

Charge-induced voltage alteration (CIVA) is a new scanning electron microscopy technique developed to localize open conductors, on both passivated and depassivated ICs. CIVA overcomes the limitations usually encountered in localizing open conductors. CIVA images are produced by monitoring the voltage fluctuations of a constant current power, supply as an electron beam is scanned over the IC surface. Contrast variations in the CIVA images are generated only from the electrically open portion of a conductor. Because of this high selectivity, CIVA facilitates localization of open interconnections on an entire IC in a single, unprocessed image. The equipment needed to implement CIVA and examples of applying the technique to several failed CMOS ICs are described. Possible irradiation effects and methods to minimize them are also discussed.<<ETX>>

IC failure analysis: techniques and tools for quality and reliability improvement

Abstract Failure analysis is an important function for integrated circuit manufacturing. It provides information necessary for technology advacement and for corrective action to improve quality and reliability. In this article the role of failure analysis is discussed, common and new techniques and tools are reviewed, and oppurtunities for the future are considered.

IC failure analysis tools and techniques-magic, mystery, and science

This review includes a discussion of the advances being made to meet the challenges presented by state-of-the-art IC and packaging technologies, since these provide the motivation and direction for the future of FA. New capabilities are required for ICs with features such as additional interconnection layers, power distribution planes, or flip chip packaging that reduce or prevent the use of conventional methods without destructive deprocessing. To support improved time to market and yield enhancement, the industry needs diagnostic techniques that provide logical and physical localization in real time during production testing.

Internal current probing of integrated circuits using magnetic force microscopy

A model for the magnetic force microscopy (MFM) imaging of IC currents is presented. MFM signal generation is described and the ability to analyze current direction and magnitude with a sensitivity of approximately 1 mA DC and approximately 1 mu A AC is demonstrated. Experimental results are a significant improvement over the 100 mA AC resolution previously reported using an electron beam to detect IC currents.<<ETX>>

Magnetic force microscopy/current contrast imaging: a new technique for internal current probing of ICs

Abstract This invited paper describes recently reported work on the application of magnetic force microscopy (MFM) to image currents in IC conductors [1]. A computer model for MFM imaging of IC currents and experimental results demonstrating the ability to determine current direction and magnitude with a resolution of ∽ 1 mA dc and ∽ 1 μA ac are presented. The physics of MFM signal generation and applications to current imaging and measurement are described.

Post-Gate Plasma and Sputter Process Effects on the Radiation Hardness of Metal Gate CMOS Integrated Circuits

The compatibility of several post-gate plasma and sputtering processes with radiation-hardened CMOS processing has been investigated. Plasma etching, plasma ashing, RF sputter etching, and DC magnetron sputtering were found to cause little effect on the threshold voltage shifts observed on CMOS inverters under gamma irradiation. However, passivation of CMOS integrated circuits with reactive-plasma-deposited SiNx films causes severe postirradiation threshold shifts. The dependence of these threshold shifts on SiNx thickness, deposition parameters, and postdeposition anneals has been characterized. Intervening CVD films between the metal layer and the SiNX have a significant effect and in some cases reduce the observed threshold shifts considerably. The observed threshold shifts do not appear to be related to the stress of the SiNx films.