Jerry M. Soden

Defect classes-an overdue paradigm for CMOS IC testing

The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

IDDQ testing: A review

Quiescent power supply current (IDDQ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of IDDQ testing. Next, the use of IDDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.

Quiescent power supply current measurement for CMOS IC defect detection

Quiescent power supply current (I/sub DDQ/) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, I/sub DDQ/ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer test vectors than a stuck-at test set. Individual CMOS ICs from three different fabrication sites had a unique pattern or fingerprint of elevated I/sub DDQ/ states for a given test set. When I/sub DDQ/ testing was added to conventional functional test sets, the percentage increase in failures ranged from 60% to 182% for a sample of microprocessor, RAM, and ROM CMOS ICs. >

Electrical properties and detection methods for CMOS IC defects

CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and I/sub DDQ/ test strategies, no single method guarantees detection of all types of CMOS defects. The I/sub DDQ/ test is the most sensitive and comprehensive, but can miss certain open-circuit defects and is a relatively slow measurement technique. The test-vector approach detects fewer of the CMOS defects, but can run at fast clock rates to detect certain open-circuit faults that may not be detectable by the I/sub DDQ/ test. Maximal CMOS IC defect detection involves a mixed-mode strategy of I/sub DDQ/ tests and vector stimulus/response tests.<<ETX>>

Test Considerations for Gate Oxide Shorts in CMOS ICs

Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-Å range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC. A 100-percent stuck-at fault test set is effective only if each test vector is accompanied by an IDD measurement. This article examines the need for a fast, sensitive method of measuring IDD during each test vector and discusses problems confronting CMOS IC designers, test engineers and test instrumentation designers as they work to meet these demands.

CMOS IC stuck-open-fault electrical effects and design considerations

The authors evaluate CMOS IC stuck-open-fault electrical effects, including voltage levels, quiescent power supply current (I/sub DDQ/), transient response, and important testing considerations. The transient responses of the defective node voltage and power supply current to the high-impedance state caused by a stuck-open defect were measured to determine if the I/sub DDQ/ measurement technique could detect stuck-open faults. The measured transient response of stuck-open faults shows that this defect acts as a memory fault for normal system and tester clock periods. The data also show that detectable elevated I/sub DDQ/ can occur rapidly for some circuit designs. Elevated I/sub DDQ/ can also occur over many clock cycles as the high-impedance node associated with the stuck-open fault undergoes a drift in its voltage. The I/sub DDQ/ technique is interpreted as significantly enhancing the detection of stuck-open defects, but not guaranteeing their detection. Modifications to the circuit layout to reduce the probability of stuck-open-fault occurrence are presented.<<ETX>>

THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS

The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.

IC failure analysis: techniques and tools for quality reliability improvement

The role of failure analysis is discussed. Failure analysis techniques and tools, including electrical measurements, optical microscopy, thermal imaging analysis, electron beam techniques, light emission microscopy, ion beam techniques, and scanning probe microscopy, are reviewed. Opportunities for advances in the field of IC failure analysis are considered. >

Parametric failures in CMOS ICs - a defect-based analysis

Defect-based test studies have thoroughly characterized CMOS IC hard bridge and open defects while less is known about a third class called parametric failures. These are more difficult to detect, and their presence is growing in CMOS IC nanoelectronics. The objective of this work is to present data that encompass the electronic properties of parametric failures that affect our ability to test present and future CMOS ICs. While parametric failures are widely reported, we seek to classify these failures with supporting data. Solutions to this complex test problem require that we structure and formalize their behaviors. Data indicate that multiparameter test strategies have the best match to some of the failures while good test strategies do not exist for others.

I/sub DDQ/ testing: issues present and future

I/sub DDQ/ testing has emerged from a company specific CMOS IC test technology in the 1960s and 1970s to become a worldwide accepted technique that is a requirement for low defective parts per million levels and failure rates. It is the single most sensitive test method to detect CMOS IC defects, and an abundance of studies have laid a solid foundation for why this is so. The I/sub DDQ/ test uses the quiescent power supply current of logic states as an indication of defect presence. Its major requirement for maximum efficiency is that the design implement nanowatt power levels (nanoampere supply current) in the quiescent portion of the power supply current. No direct connections are allowed between V/sub DD/ and V/sub SS/ during the quiescent period. I/sub DDQ/ testing has increased significantly since 1990, highlighting problems and driving solutions not addressed by the high reliability manufacturers of earlier technologies. Faster I/sub DDQ/ instrumentation and better software tools to generate and grade I/sub DDQ/ test patterns result from this increased interest. We address two major issues confronting I/sub DDQ/ testing: yield loss and increased background current of deep submicron IC technologies projected by the Semiconductor Industry Association/Sematech road map. Both issues are points of controversy.