Christy S. Tyberg

Design and Modeling Methodology of Vertical Interconnects for 3DI Applications

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm.

Generation of local magnetic fields at megahertz rates for the study of domain wall propagation in magnetic nanowires

We describe a technique for generating local magnetic fields at megahertz rates along magnetic nanowires. Local and global magnetic fields are generated from buried copper fine-pitch wires fabricated on 200mm silicon wafers using standard complementary metal-oxide-semiconductor back-end process technology. In combination with pump-probe scanning Kerr microscopy, we measure the static and dynamic propagation fields of domain walls in permalloy nanowires.

Thermal analysis of multi-layer functional 3D logic stacks

3D chip stacking technology has the potential to enable increased system performance through integration of heterogeneous system components, such as accelerators and high density memory, as well as through increased area for tightly integrated processor components in multi-core systems. This paper describes the design, measurements and a thermal modeling methodology used to achieve accurate 3D thermal model-to-hardware correlation for two and three layer 3D high-power “logic” stacks.

3D integration ESD protection design and analysis

A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection.

Assembly and packaging of non-bumped 3D chip stacks on bumped substrates

In this paper, a novel assembly and packaging approach is proposed for 3D/2.5D chip stacks based on bumped substrates. The thinned chips are stacked using thermal compression bonding with “flat” metallization to reduce assembly complexity associated with conventional controlled-collapse-chip-connection (C4) solder bumps. Meanwhile, the laminate substrates are bumped with C4s using injected molten solder (IMS) processes. The pre-stacked chips are then assembled and packaged on the bumped laminates successfully.

Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks

3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficulties associated with the stacking of medium and large logic dies with fine pitch copper pillar bumps is discussed, including mass reflow and thermo-compression bonding on 3 and 4 layers chip stacks.

TSV/FET proximity study using dense addressable transistor arrays

Addressable transistor arrays (~20,000 devices) provide an attractive test vehicle to study TSV/FET proximity effects in a statistically meaningful way. FET/TSV proximity effect studies have been performed at the 45 nm node using a dense addressable parametric diagnostic (APD). We have found that a carefully designed TSV integration sequence at this node has minimal impact on the quality of devices. For the integration scheme studied, it was found that stress of the Si in the vicinity of the TSV had minimal impact on device characteristics for annular Cu TSVs, for devices placed as close as ~3μm to the TSV.