Raphael Robertazzi

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 TM microprocessor

Integrated voltage regulator modules (iVRMs) [1] provide a cost-effective path to realizing per-core dynamic voltage and frequency scaling (DVFS), which can be used to optimize the performance of a power-constrained multi-core processor. This paper presents an iVRM system developed for the POWER8™ microprocessor, which functions as a very fast, accurate low-dropout regulator (LDO), with 90.5% peak power efficiency (only 3.1% worse than an ideal LDO). At low output voltages, efficiency is reduced but still sufficient to realize beneficial energy savings with DVFS. Each iVRM features a bypass mode so that some of the cores can be operated at maximum performance with no regulator loss. With the iVRM area including the input decoupling capacitance (DCAP) (but not the output DCAP inherent to the cores), the iVRMs achieve a power density of 34.5W/mm2, which exceeds that of inductor-based or SC converters by at least 3.4× [2].

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

POWER8™ is a 12-core processor fabricated in IBMs 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.

New tools and methodology for advanced parametric and defect structure test

Continuing scaling trends in semiconductor technology, as well as the test requirements of new technologies being incorporated with mainstream silicon integrated circuits, has increased the complexity of parametric and defect structure testing. New testers are required which can drastically improve the throughput of parametric test, as well as efficiently test new array based process diagnostic structures. Addressing these needs requires merging the traditionally separate functions of digital and parametric test equipment. We describe the development of a new hybrid test system, which combines the features of parametric and digital testers, and in addition introduces a high degree parallelism in its parametric test functions. The test system was developed for high throughput inline test (“parallel test”) of defect structures, semiconductor parametric macros, and advanced array based process monitors down to pA current levels, as well as traditional all digital yield macros, such as SRAMs.

Analytical MRAM test

Magnetic Random Access Memory (MRAM) is a new technology which offers a viable alternative to other forms of nonvolatile memory, such as flash, where read access time, writing speed, and cell endurance is at a premium. Difficulties in scaling DRAM below the 32nm node may make MRAM a suitable candidate for DRAM replacement. The rigors of MRAM cell development present array designers, process engineers, and test engineers with many unique challenges. Enabling process development through test support of defect monitors makes test development particularly difficult in MRAM technology, due to the complexity of highly nonlinear magnetic materials and device behaviors. We review a number of new strategies and methodologies employed to support MRAM cell development over several MRAM generations, in a research environment. A unique test system with both advanced digital and parametric capabilities will be described. The importance of database integration within the test software and real-time data analysis will also be discussed.

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

We have reported previously (Pong-Fei Lu et al., 2004) a low-swing latch (LSL) with superior performance-power tradeoff compared to the conventional pass-gate master-slave latch. In this paper, hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system power in high-frequency microprocessors. We have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle between two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system power saving can be achieved in pulsed mode compared to non-pulsed mode. Power contribution from individual components is also presented

A low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

We report A new low-swing latch (LSL) for low-power applications. Unlike the conventional transmission gate latch, the LSL allows reduced voltage on the clock inputs. Therefore the local clock buffer (LCB) can use reduced swing to save power while all other circuits are running at nominal voltage. We have implemented an accumulator loop experiment in an early version of IBMs 90 nm SOI technology on a testchip. The experiment consists of an adder and a decrementer surrounded by latches to mimic logic between pipeline stages. Side-by-side comparisons between the transmission gate latch and LSL are designed to illustrate the superior power-performance tradeoff of the LSL approach. Hardware measurements have shown 12% AC power saving in 90 nm technology.

Thermal analysis of multi-layer functional 3D logic stacks

3D chip stacking technology has the potential to enable increased system performance through integration of heterogeneous system components, such as accelerators and high density memory, as well as through increased area for tightly integrated processor components in multi-core systems. This paper describes the design, measurements and a thermal modeling methodology used to achieve accurate 3D thermal model-to-hardware correlation for two and three layer 3D high-power “logic” stacks.

Assembly and packaging of non-bumped 3D chip stacks on bumped substrates

In this paper, a novel assembly and packaging approach is proposed for 3D/2.5D chip stacks based on bumped substrates. The thinned chips are stacked using thermal compression bonding with “flat” metallization to reduce assembly complexity associated with conventional controlled-collapse-chip-connection (C4) solder bumps. Meanwhile, the laminate substrates are bumped with C4s using injected molten solder (IMS) processes. The pre-stacked chips are then assembled and packaged on the bumped laminates successfully.

Analyzing path delays for accelerated testing of logic chips

We develop a test methodology utilizing the critical path delay to monitor and predict the degradation of circuits during a ramp voltage stress (RVS). Stress is applied by looping functional patterns during RVS. Our results demonstrate that the degradation behavior of a functional circuit can be characterized and analyzed with RVS in a manner similar to that developed for a single transistor. This alternative fast test lends itself to in-line testing with reduced times and small sample numbers.

TSV/FET proximity study using dense addressable transistor arrays

Addressable transistor arrays (~20,000 devices) provide an attractive test vehicle to study TSV/FET proximity effects in a statistically meaningful way. FET/TSV proximity effect studies have been performed at the 45 nm node using a dense addressable parametric diagnostic (APD). We have found that a carefully designed TSV integration sequence at this node has minimal impact on the quality of devices. For the integration scheme studied, it was found that stress of the Si in the vicinity of the TSV had minimal impact on device characteristics for annular Cu TSVs, for devices placed as close as ~3μm to the TSV.