Yih-Peng Chiou

A New Model for Through-Silicon Vias on 3-D IC Using Conformal Mapping Method

Based on the conformal mapping technique, a novel macro- π model is proposed to accurately predict the electrical performance of a low pitch-to-diameter ratio (P / D) through-silicon via (TSV) pair on the 3-D IC. The model combines the conventional resistance and inductance (RL) circuit with several parallel capacitances and conductance (CG) circuit. The accuracy-improved CG model rigorously considers the proximity effect. The model can be established by using the derived closed-form formula that is related to geometrical parameters of the TSVs. Compared with the conventional π-type model, the proposed model can significantly reduce the error of CG value from 25% to 2% with respect to a full-wave simulation, and thus the insertion loss can be well predicted from dc to 40 GHz.

Bandwidth Enhancement Based on Optimized Via Location for Multiple Vias EBG Power/Ground Planes

The ground surface perturbation lattice (GSPL) structure is investigated to suppress power noise in the power distribution network of mixed signal circuits. In order to enhance the bandwidth of the noise suppression, the GSPL structure is implemented by using multiple vias in the mushroom-like electromagnetic bandgap structure. Under the concept of multiple vias, the lower and upper bound cutoff frequencies of the bandgap are influenced by the position of the vias. An optimum position for the vias is found to achieve maximum stopband bandwidth. In this paper, the stopband mechanism of GSPL structure is investigated and the corresponding equivalent circuit model is proposed to quickly predict the lower and upper bound cutoff frequencies. Suitable test boards are fabricated and measured to demonstrate the accuracy of the design concept. The result shows that there is a good consistency between simulated, modeled, and measured results.

ABF-Based TSV Arrays With Improved Signal Integrity on 3-D IC/Interposers: Equivalent Models and Experiments

An Ajinomoto-Build-up-Film (ABF) material is proposed to manufacture through-silicon vias (TSVs) with better signal integrity and lower cost than that of conventional TSVs. The unique advantage of the ABF-based TSVs is that the isolation layer can be thicker than the conventional TSVs, and thus both the insertion loss and crosstalk of the ABF-based TSVs can be improved. An equivalent circuit model is given to predict the electrical behavior of the TSVs and to explain how ratio of the isolation layers thickness to the radius affects the signal integrity. The concept is demonstrated both in frequency- and time-domain simulations. Finally, a test sample of nine-stack ABF-based TSVs is fabricated and assembled. The scanning electron microscope figure supports that the ABF-based TSVs have a thickness-to-radius ratio of 0.667, which is much higher than the conventional TSVs ratio of about 0.1. The measurements also support the simulated results from the equivalent circuit model.

Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.

A Circular-Ring Miniaturized-Element Metasurface With Many Good Features for Frequency Selective Shielding Applications

A novel circular-ring miniaturized-element (CRME) metasurface is proposed for frequency selective electromagnetic shielding applications in this paper. The proposed structure exhibits good performance in many aspects. The CRME size can be easily reduced to 0.088 λr × 0.088 λr, where λr is the wavelength at resonance. Such small size can be useful in applications with limited space. The newly proposed metasurface not only shows the stability to incidence angles and polarizations, but also demonstrate negligible polarization crossing. The metasurface also presents low coupling between elements, which leads to the insensitivity of periodicity fluctuation in fabrication process. Moreover, the frequency responses can be varied through the modification of the element pattern of the metasurface. It provides flexible frequency responses to use in frequency selective shielding applications. Also, this element is suitable for constructing a metasurface aligned in either square or even hexagonal lattice, which owns the best adaptability to a doubly curved surface or a spherical one. Without revising the CRME, both the squareand hexagonal-lattice metasurfaces constructed can perform competently at the same time. Finally, the metasurface prototype is fabricated and tested in a fully anechoic chamber to verify the design. The measured results well agree with the simulated ones.

3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures

Substrate coupling in 3-D-ICs using Cu through silicon vias (TSVs) is a predicament widely documented in recent literature. Yet, discussions remain limited to the electromagnetic framework, such that a complete understanding of noise propagation and absorption is hampered. This letter thoroughly examines these phenomena in the TSVs from the integrated perspectives of semiconductor physics and electromagnetic theory and investigates the noise reduction method using the combination of p+ guard-ring and grounded TSV via 3-D device simulation.

A novel TSV model considering nonlinear MOS effect for transient analysis

A novel equivalent circuit model of through-silicon via (TSV) considering the time-dependent capacitance due to metal-oxide-semiconductor (MOS) effect has been proposed. This model can characterize the variance of capacitance between metal and silicon substrate caused by the differential change of depletion region width as the voltage applied on the TSV changes with time. Compared to conventional TSV models, the capacitance has a 70% difference when the TSVs applied voltage transits from low state to high state. Besides, 3% difference of eye height and 100% difference of eye jitter can be observed in eye diagram by SPICE simulation.

Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.

Very Closely Located Dual-Band Frequency Selective Surfaces via Identical Resonant Elements

Very closely located dual-band frequency selective surfaces (FSSs) are proposed in this letter. The ratio of two operating bands can be as low as 1.06. The proposed FSSs comprise simply a single-layer metallic pattern on a thin dielectric substrate. The mechanism to achieve the low ratio between two operating bands is attributed to two separated resonant modes caused by four identical elements in a unit cell. Asymmetrical meandered pattern is introduced to improve stability of frequency responses with respect to incident angles. Moreover, the ratio of the operating bands can be tuned through rotation of the elements with ratios in the range from 1.06 to 1.10. In order to validate the designs, the prototype of the dual-band FSSs has been fabricated and tested. And the measured results show good agreements with the simulated ones.

3D simulation of substrate noise coupling from Through Silicon Via (TSV) and noise isolation methods

This paper presents simulation results of substrate noise coupling between through silicon via (TSV) and MOSFET. Electrical noise coupling through coexistence of junction capacitances and threshold modulation in substrate is studied and discussed through 2D and 3D transient analyses in this paper. Furthermore, noise isolation methods including guard rings and grounded shield TSV are incorporated to improve the noise decoupling and are examined to verify their effectiveness.