Chuguang Feng

A high-density conduction-based micro-DNA identification array fabricated with a CMOS compatible process

A high-density CMOS-compatible deoxyribonucleic acid (DNA) array fabricated with a modified metallization process is demonstrated. The array consists of silicon nitride isolation to confine the DNA sample to a specific cell area defined by silicon dioxide to achieve low crosstalk between neighboring cells. A prehybridization process together with a conductive enhancement method are also developed to improve the signal to noise ratio. Nine orders of magnitude difference in conductance is measured between array cells with matched and single-based mismatched DNA samples. The matching of DNA molecules can then be easily detected by a simple digital switching circuit.

A three-dimensional stacked fin-CMOS technology for high-density ULSI circuits

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.

Stacked 3-D Fin-CMOS technology

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.

Three-dimensional stacked-Fin-CMOS integrated circuit using double layer SOI material

In this work, a stacked 3D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2D architecture; (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2D CMOS technology. To implement the 3D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.

An elevated source/drain-on-insulator structure to maximize the intrinsic performance of extremely scaled MOSFETs

Abstract In this paper, a source/drain structure separated from the silicon substrate by oxide isolation is fabricated and studied. The source/drain diffusion regions are connected to the shallow source/drain extension through a smaller opening defined by a double spacer process. Experimental results indicate that the source/drain on insulator significantly reduces the parasitic capacitance. Further optimization by simulation indicates a reduction of series resistance and band-to-band drain leakage at off-state can be achieved in extremely scaled devices. Compared with the conventional planner source/drain structure, the reduction of parasitic capacitance and series resistance can be as much as 80% and 30% respectively.

A high density conduction based micro-DNA-identification array fabricated in a CMOS compatible process

A high-density CMOS-compatible DNA array fabricated using a modified metalization process is demonstrated. The array produces a conductivity difference of nine orders of magnitude for matched and single-based mismatched DNA molecules, which can be easily detected by a simple sensing circuit.

Novel Localized-SOI MOSFET's Combining the Advantages of SOI and Bulk Substrates for Highly-Scaled Devices

In this paper two kinds of novel localized-SOI structure devices, named as Quasi-SOI MOSFET and source-drain -on-nothing(SDON)/source-drain-on-insulator (SDOI) MOSFET, are demonstrated which can combine the advantages of SOI and bulk substrates. In the Quasi-SOI structure with the source/drain regions quasi-surrounded with insulator and the channel region directly connected with the bulk substrate, short channel effects (SCE), parasitic capacitance and self-heating effects (SHE) can be effectively reduced. The problem of degraded mobility and increased threshold voltage due to ultra-thin body in UTB SOI MOSFETs can also be solved. A method to fabricate the Quasi-SOI MOSFET is put forward. Process-device co-simulation results further show good scaling capability and excellent heat dissipation of the Quasi-SOI devices. In the SDON/SDOI device with the recessed S/D extension regions and source-drain staying on the partially buried layers, the advantages of quasi-SOI MOSFET can be maintained with the parasitic capacitance further reduced and the fabrication technology basically compatible with the standard CMOS technology. The proposed two structures can be considered as good candidates for highly-scaled devices.

A study of source/drain-on-insulator structure for extremely scaled MOSFETs

As MOSFET feature sizes are scaled to the deep sub-0.1 /spl mu/m regime, ultra-shallow source/drain extensions and heavily doped halos are required to suppress short-channel effects. These structures result in high series resistance and parasitic capacitance. A source/drain-on-insulator (SDOI) structure with elevated source/drain combined with an oxide isolation, formed by a shallow trench process underneath the source/drain region, is reported to be a potential solution to simultaneously reduce the series resistance and parasitic capacitance. However, the optimization of SDOI structures is very tricky and the tradeoff between series resistance and gate-to-drain Miller capacitance is not obvious. In this paper, the advantage of this MOSFET source/drain engineered structure is verified by detailed device simulation with extremely scaled MOSFETs. Device structure parameter optimizations are discussed to maximize the intrinsic performance. Design guidelines and potential performance gain with the SDOI structure are also discussed.

Double-gate SOI MOSFET fabrication from bulk silicon wafer

The double-gate SOI structure is believed to be the most scalable technology down to the 0.02/spl mu/m regime. However, experimental study of double-gate related phenomena has been hindered by the difficulties in fabricating double-gate devices. In this paper, a simple and yet flexible method to fabricate an experimental double-gate device is proposed. The double-gate device is actually fabricated on a silicon film recrystallized from amorphous silicon (referred as large grain polysilicon-on-insulator or LPSOI film), which is not truly single crystal SOI. However, material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in the early days. Thus, all physical properties of double gate SOI devices are preserved.