Xinnan Lin

An Analytical Charge Model for Double-Gate Tunnel FETs

An analytical charge model for double gate (DG) tunnel FETs (TFETs) is proposed. By splitting the TFET into a series combination of a gated tunnel diode and a DG MOSFET, we solved the Poisson equation with matching boundary conditions to obtain a surface potential model for the DG TFET. Based on that, the source depletion charge and the mobile channel charge are derived. Comparisons between the proposed model and TCAD simulations show good agreements and suggest a 100/0 drain/source channel inversion charge partition. Terminal capacitances calculated based on the proposed charge model are also evaluated and show good agreement with TCAD simulations.

Opposite side floating gate SOI FLASH memory cell

An opposite side floating gate SOI FLASH memory cell has been proposed for advanced device scaling. The new structure has the read gate and floating gate on the opposite sides of the active silicon film. It allows the use of a thick tunneling oxide to prevent charge leakage and a thin gate oxide for device scaling. The functionality of the device is demonstrated through the analysis of threshold voltage shift before and after programming. The effects of various parameters such as front and back gate oxide thickness, silicon film thickness and channel doping on device performance have been studied and a possible way to fabricate the device is proposed.

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.

3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies

This paper describes a method to integrate non-planar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis

A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting from the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold voltage effects are also observed in the implemented SA ESDG device.

A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability

A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model.

A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage (Vth), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well.

Derivative superposition method for DG MOSFET application to RF mixer

A high linear double-gate (DG) MOSFET application to RF mixer is proposed based on derivative superposition method which was successfully used in Bulk CMOS region. By independently biasing front and back gate voltage of DG MOSFET, one DG MOSFET device is reviewed as two parallel devices. In this way, we realize the derivative superposition method application in the DG MOSFET linearity analysis and high performance RF mixer. Via two-dimensional (2D) TCAD device simulation and through the third-order transconductance (gm3) cancellation, we get some interesting results of DG MOSFET mixer different from the Bulk CMOS mixer. It is found that the DG MOSFET is suitable to work as a single device mixer because of coupling effect of two gates, e.g., a high linear independent DG MOSFET mixer shows 7.8dB improvement on IIP3 corresponding to the symmetrical DG mixer with the same DC current. The relationships between the amplitude of LO signal, the conversion gain and linearity are also analyzed in this paper.

Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs

In this paper, a SPICE compatible analytical surface-potential-based model for junctionless symmetric double-gate (JLDG) MOSFETs is described. By using the gradual-channel-approximation, the 1-D Poissons equation is solved to obtain the surface and central potential in the JLDG MOSFET for long channel case. A continuous drain current model with smooth transitions from fully depleted region to partially depleted and accumulation regions is then derived from the Pao-Sahs dual integral as a function of the surface and central potential at the source and drain terminals. The model is verified and validated by numerical simulations over a wide range of doping concentrations and device geometries. The model has been implemented in a circuit simulator and used to simulate some circuit building blocks without any convergent problem.