Chuichi Miyazaki

Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips

The wire bonding technique has been used for conventional 3D-stacked packages. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. In this study, a method is described for interconnecting stacked chips using through-hole electrodes. Electrical interconnection between the chips is achieved by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. The basic concept of the proposed method was validated using test samples with quasi-through-hole electrodes. Application of chip-to-chip interconnection to a conventional 3D-stacked system-in-package (SiP) with an microprocessing unit (MPU) chip and an synchronous DRAM (SDRAM) chip reduced the package thickness to less than 0.5 mm from 1.25 mm and the number of layer in the package substrate to two (thickness less than 0.2 mm) from six (0.45 mm). The wiring distance between stacked chips is minimized by using an interposer chip. We formed through-hole electrodes in a 30-mum-thick silicon wafer and determined that the measured leakage with plasma CVD of SiO2 met our target specification for the electrical insulation between through-hole electrodes. Use of this method should facilitate the production of ultra-slim, high-performance SiP

Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding

To verify the operation of three-dimensional SiP with through-hole electrode interconnections, we manufactured a prototype of a 3D-SiP sample composed of a MCU, an interposer, and a synchronous DRAM (SDRAM) chip using a proposed mechanical caulking operation. A new electrode design of LSI for through-hole electrode interconnection is important for establishing a stable mass-production process. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick

Development of wafer thinning and dicing technology for thin wafer

Various stress relief and dicing methods are evaluated for 10 to 30µm wafer thickness. DP(Dry Polish) and CMG (Chemical Mechanical Grinding) are the best solution for productivity and quality in wafer thinning. Highest die strength is achieved for the blade dicing and DBG (Dicing Before Grinding) due to the decreased backside chipping in thin wafer. As for DBG, it is necessary to improve the resin adhesive strength of H-WSS (Hard Wafer Support System).

Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a ldquomechanical-caulkingrdquo technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve SiO2 etching with shorter turn around time (TATs) and high TSV yields of more than 99%.

Development of high accuracy wafer thinning and pickup technology for thin wafer(die)

Accurate wafer thinning and picking up die technology around 10μm thickness were evaluated. We obtained the prospect that thickness accuracy 10±1μm which is the target of the ultra thin grinding, by applying new technology like Non-contact gauge or Auto TTV. For picking up the ultra thin dies, we found the best tool design rule and some machine condition in slider peel method.

Development of high accuracy wafer thinning and pickup technology for thin wafer

We have evaluated accurate wafer thinning and picking up die technology around 10? m thickness. We obtained the prospect that thickness accuracy 10±1? m which is the target of the ultra thin grinding, by applying new technology like non-contact gauge or Auto TTV. The thickness distribution of the wafer with the glass achieved the sample of TTV:2.9? m, and the thickness accuracy of a real wafer became TTV:0.4? m as a result of doing BG by using non-contact gauge the Auto TTV function. Targeted value TTV:1.4? m was able to be achieved. For picking up the ultra thin dies, we found the best tool design rule and some machine condition. In picking up the ultra thin dies, the amount of the overhang of the die to the width of the slider confirmed 0.3mm was the best. The peel property of the chip edge was improved by the tension to horizontal direction in enlarging the amount of the tape expansion and picking up was improved. In addition, the peel property of the chip edge improved by slowing down the slider speed when beginning.

Study for CMOS device characteristics affected by ultra thin wafer thinning

Wafer thinning and fabrication of through-Si via (TSV) and micro-bump are key processes in 3D LSI. Because of mechanical stress under these processes, electrical deviations of CMOS devices such as DRAM are occurred. And the other hand, the thinner Si chip becomes, the more risky impurity ion contamination attacks the Si device. We will report about the result of DRAM retention time reduced to one third by Cu contamination whose thickness is less than 50μm. And also report about the example for investigation of several gettering methods.