Seong-Soon Cho

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology

An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.

Low voltage high speed circuit designs for giga-bit DRAMs

An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.

A New Cell-Type String Select Transistor in NAND Flash Memories for under 20nm Node

A new string structure, having a cell-type string select transistor line (CT-SSL) is proposed for NAND flash memories beyond 20nm node device. The boosted potentials at a program-inhibited active line were measured with the CT-SSL and compared with the potential measured with a conventional SSL at 4Xnm, 2Xnm, and 1Xnm node devices. The boosted channel potentials were not degraded by drain-induced-barrier-lowering (DIBL) even when using one cell WL as a SSL. As-dopant diffused length by source/drain N+ implantation (S/D N+ IIP) was simulated to determine the minimum required gate length of a SSL. The newly proposed CT-SSL can successfully replace the conventional SSL.

An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme

An area-efficient packet-based 256 Mb DRAM with a 4 bank architecture and a peak bandwidth of 1.0 Gbps/pin at V/sub cc/=2.35 V, Temp=100/spl deg/C is developed. This chip features a daisy chained redundancy scheme, an area-efficient logic block placement and routing technique and a process insensitive DLL with duty error reduction scheme to overcome large chip size penalty and to improve chip yield.

A 2.5 V, 2.0 GByte/s packet-based SDRAM with a 1.0 Gbps/pin interface

A 2.5 V, 72 Mbit packet protocol based SDRAM (PSDRAM) achieving a peak bandwidth of 2.0 GByte/s has been developed with a 0.23 /spl mu/m twin-well, 4-poly, 2-metal CMOS process. An internal Vcc of 2.0 V and V/sub term/ of 1.8 V with 0.8 V signal swing are used in the array to reduce the sensing power and I/O switching power, respectively. The total maximum chip power consumption of 1.80 W, including the average I/O switching power of 0.25 W, has been achieved when internal 16 banks are interleavingly operated with 20 ns interval commands at 2.0 GByte/s, Vcc=2.7 V, and T=25/spl deg/C.