Chun-Hao Chou | Researchain

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Featured researches published by Chun-Hao Chou.

international electron devices meeting | 2010

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

C.C. Wu; Derek Lin; A. Keshavarzi; Chien-Chao Huang; C.T. Chan; Chien-Hsien Tseng; Chen-Shien Chen; Cheng-chieh Hsieh; King-Yuen Wong; M.L. Cheng; T.H. Li; You-Ru Lin; L.Y. Yang; Chia-Pin Lin; Chuan-Ping Hou; Hung-Ta Lin; J.L. Yang; K.F. Yu; Ming-Jer Chen; T.H. Hsieh; Y.C. Peng; Chun-Hao Chou; C.J. Lee; Cheng-Chuan Huang; C.Y. Lu; F.K. Yang; Hung-Wei Chen; L.W. Weng; P.C. Yen; S.H. Wang

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent Vth roll-off immunity in the short-channel regime that allows properly positioning the long-channel device Vth. Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

international electron devices meeting | 2015

Optical performance study of BSI image sensor with stacked grid structure

Yun-Wei Cheng; Tsung-Han Tsai; Chun-Hao Chou; Kuo-Cheng Lee; Hsin-chi Chen; Yung-Lung Hsu

Stacked grid structure is implemented into back-side illumination (BSI) image sensors and device performance for various grid design including dimension and height has been investigated. Simulated angular response shows less quantum efficiency (QE) degradation in large incident angle and SNR-10 has a ~10% improvement for devices with stacked grid structure.

Archive | 2010