Yung-Lung Hsu | Researchain

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Featured researches published by Yung-Lung Hsu.

international electron devices meeting | 2016

Ultra-low-resistance 3D InFO inductors for integrated voltage regulator applications

Chen-Shien Chen; Yung-Lung Hsu; Jeng-Shien Hsieh; Ching-Wei Tsai; Victor C. Y. Chang; A. Roth; E. Soenen; C.-T. Wang; Douglas Yu

A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm3. It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mu. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.

international electron devices meeting | 2015

Optical performance study of BSI image sensor with stacked grid structure

Yun-Wei Cheng; Tsung-Han Tsai; Chun-Hao Chou; Kuo-Cheng Lee; Hsin-chi Chen; Yung-Lung Hsu

Stacked grid structure is implemented into back-side illumination (BSI) image sensors and device performance for various grid design including dimension and height has been investigated. Simulated angular response shows less quantum efficiency (QE) degradation in large incident angle and SNR-10 has a ~10% improvement for devices with stacked grid structure.

Archive | 2017