Chun-Jung Su

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

Novel poly-silicon nanowire field effect transistor for biosensing application

A simple and low-cost method to fabricate poly-silicon nanowire field effect transistor (poly-Si NW FET) for biosensing application was demonstrated. The poly-silicon nanowire (poly-Si NW) channel was fabricated by employing the poly-silicon (poly-Si) sidewall spacer technique, which approach was comparable with current commercial semiconductor process and forsaken expensive E-beam lithography tools. The electronic properties of the poly-Si NW FET in aqueous solution were found to be similar to those of single-crystal silicon nanowire field effect transistors reported in the literature. A model biotin and avidin/streptavidin sensing system was used to demonstrate the biosensing capacity of poly-Si NW FET. The changes of I(D)-V(G) curves were consistent with an n-type FET affected by a nearby negatively (streptavidin) and positively (avidin) charged molecules, respectively. Specific electric changes were observed for streptavidin and avidin sensing when nanowire surface of poly-Si NW FET was modified with biotin and streptavidin at sub pM to nM range could be distinguished. With its excellent electric properties and the potential for mass commercial production, poly-Si NW FET can be a very useful transducer for a variety of biosensing applications.

A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel

A very simple and low-cost scheme is proposed for fabricating thin-film transistors with poly-Si nanowire (NW) channels. In this scheme, the poly-Si NW channel is formed by cleverly employing the poly-Si sidewall spacer technique. In addition, the poly-Si NW channel is genuinely exposed to the environment after the poly-Si sidewall spacer formation in the new scheme. This unique feature, together with its simplicity and low-cost, makes this approach very suitable for applications and manufacturing of bio-logic sensing devices. Good device performance is demonstrated in this letter.

Ultrasensitive detection of dopamine using a polysilicon nanowire field-effect transistor

An unprecedented high sensitive sensing of neurotransmitter dopamine at fM level was demonstrated using a poly-crystalline silicon nanowire field-effect transistor (poly-SiNW FET) fabricated by employing a simple and low-cost poly-Si sidewall spacer technique, which was compatible with current commercial semiconductor processes for large-scale standard manufacture.

High-performance TFTs with Si nanowire channels enhanced by metal-induced lateral crystallization

Thin-film transistors with poly-Si nanowire (NW) channels enhanced by metal-induced lateral crystallization (MILC) are reported. The new device features a side-gate with self-aligned NW channels abutting the sidewalls of the gate structure. By adopting the MILC technique, the crystallinity of the NW channels is greatly enhanced, compared to those formed by solid-phase crystallization. As a result, the electrical performance of the devices could be significantly enhanced in terms of reduced subthreshold swing and threshold voltage as well as improved field-effect mobility.

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single- gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.

Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

In this study, a novel multiple-gated (MG) thin-film transistor (TFT) with poly-Si nanowire (NW) channels is fabricated using a simple process flow. In the proposed new transistors, poly-Si NWs were formed in a self-aligned manner and were precisely positioned with respect to the source/drain, and the side-gate. Moreover, the NW channels are surrounded by three gates, i.e., top-gate, side-gate and bottom-gate, resulting in much stronger gate controllability over the NW channels, and greatly enhanced device performance over the conventional single-gated TFTs. Furthermore, the independently applied top-gate and/or bottom-gate biases could be utilized to adjust the threshold voltage of NW channels in a reliable manner, making the scheme suitable for practical applications.

Water passivation effect on polycrystalline silicon nanowires

Defects present in the grain boundaries of polycrystalline materials are known to impede carrier transport inside the materials, and the electronic device performance having such materials as active channels will be adversely affected. In this work, dramatic improvement in device performance was observed as field-effect transistors with polycrystalline silicon nanowire (poly-SiNW) channels were exposed to a wet environment. Passivation of defects in the poly-SiNW by H+ and/or OH− contained in the aqueous solution is proposed to explain the phenomenon.

A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

Operation of a Novel Device With Suspended Nanowire Channels

We investigate the operation of a new device featuring a side-gate scheme and suspended poly-Si nanowire (NW) channels. The fabrication adopted a sidewall-spacer-etching technique to form the poly-Si NW channels. The NW channels were further suspended using a simple wet-etching step. An interesting hysteresis phenomenon is observed in the I-V characteristics. In addition, a steep subthreshold swing (< 60 mV/dec) is also observed in the transfer curves. A scenario is proposed to explain the operation of such a device.