Tzu-I Tsai

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

Channel Thickness Effect on High-Frequency Performance of Poly-Si Thin-Film Transistors

In this letter, we present the high-frequency performances of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a nominal gate length of 0.22 μm. Owing to the short gate length and adoption of salicide process, cutoff frequency (fT) of 17 GHz and maximum oscillation frequency of ~ 21 GHz are obtained. The result suggests that the poly-Si TFT technology is applicable to RF integrated circuits up to 2 GHz. In addition, we also investigate the effects of channel thickness on the high-frequency characteristics of poly-Si TFTs. We find that the variation of fT with channel thickness is mainly due to the change in transconductance.

Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique

In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al2O3 gate stack using an implant-free approach. Since the source/drain and channel regions are sharing one in situ phosphorous-doped poly-Si material, the process flow and cost could be efficiently reduced. Owing to the GAA configuration and small volume of NW channels, the fabricated devices with heavily doped channels display superior switching behaviors and excellent immunity to short-channel effects. Besides, the negative fixed charges in Al2O3 are found to be helpful to obtain desirable positive threshold voltages for the n+-poly-Si channel devices. Thus, the simple and low-cost fabrication method along with excellent device characteristics makes the proposed GAA NW transistor a promising candidate for future 3-D electronics and system-on-panel applications.

Low-Operating-Voltage Ultrathin Junctionless Poly-Si Thin-Film Transistor Technology for RF Applications

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of 8 × 107. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 μm exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (fmax) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications.

Low temperature polycrystalline Si nanowire devices with gate-all-around Al 2 O 3 /TiN structure using an implant-free technique

In this work, for the first time, we propose and demonstrate an implant-free gate-all-around (GAA) low-temperature poly-Si (LTPS) nanowire (NW) device with Al2O3 dielectric and TiN gate. Since the channel and source/drain (S/D) regions are sharing one in-situ phosphorous-doped poly-Si material, the process cost could be efficiently reduced. Such novel scheme appears to be promising for both system-on-panel (SOP) and three dimensional IC applications. High on-off current ratio and on-state performance are demonstrated for the new device.

Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique

The authors present a simple double patterning technique with I-line stepper to define nanoscale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-100-nm gate length. With this approach, polycrystalline silicon (poly-Si) gate with linewidth down to 80 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography. Moreover, ineffectiveness of end point detection in the second poly-Si gate definition is also addressed. For reliable process control in the second etching step, appropriate mask design is found to be essential. Finally, sub-100-nm MOSFETs with or without halo implemented symmetrically or asymmetrically are fabricated and characterized.

A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal–oxide-semiconductor field-effect transistors. Excellent device characteristics were verified.

Reliability of strained-channel NMOSFETs with SiN capping layer on hi-wafers with a thin LPCVD-TEOS buffer layer

The local strained channel (LSC) technique is proposed to provide tensile strained channel in nMOSFETs. However, the device reliability associated with the strained device owing to the strain, and excess hydrogen and nitrogen incorporation from the deposited SiN layer is an imminent concern. In line with this, the incorporation of a thin LPCVD-TEOS buffer layer to improve the reliability performance has been proposed. In addition, hydrogen annealed wafers (Hi-wafer) have been reported having reduced oxygen defects in Czochralski (CZ) wafers, with improved microroughness and defect on the surface after high hydrogen annealing.