Chun-Sup Kim

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V/sub cc/=3.3 V and T=25/spl deg/C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.

A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, t/sub AA/ /t/sub RCD//t/sub RP/ of 3/3/3 at 533 Mb/s are achieved in the design. For signal integrity at 533 Mb/s, off-chip driver calibration and on-die termination are employed.

A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system

In a memory system employing wide channel high-performance DRAMs, skews resulting from nonideal system and chip environments become the most critical factor. This 256 MB memory system achieves 256 Gb/s peak bandwidth with a 160 MHz clock and 64b channel using a /spl plusmn/0.4 V-swing, push-pull type I/O interface (SSTL).

A CMOS 4/spl times/ speed DVD read channel IC

Optical disk is a data storage medium of the highest density, and is widely used for compact disk and digital versatile disk (CD/DVD) players and read-only memory and random-access memory (ROM/RAM) drives. In this work, all functions for 1/spl times/ speed DVD read channels are integrated on a single 0.8-/spl mu/m CMOS chip. A ninth-order pulse slimming equalizer with two zeros is made programmable to cover a frequency range of over five octaves from 0.7 to 25 MHz with high-frequency boost of 12 db and group delay variation of less than /spl plusmn/3%. A one-beam tracking error detector features six allpass delay equalizers with a tunable delay range of 93 ns at 2 MHz. Other control functions integrated on the chip are three-beam tracking error generator, laser power control circuit, and detectors for track crossing, disk defect, signal envelope, focus error, etc. The chip occupies 25 mm/sup 2/ and consumes 500 mW at 5 V.

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface

A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using (1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, (2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and (3) a flexible column redundancy scheme to efficiently increase redundancy coverage using a shifted I/O line scheme for multibank architecture.

A 1.0 V 256 Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes

A 1.0 V, 256 Mb SDRAM is designed in a 0.1 /spl mu/m CMOS technology. For low voltage applications, an offset compensated direct current sensing scheme improves refresh time as well as sensing performance. A charge-recycled precharge reuses the word-line discharge current to generate the boosted voltage required for equalization without charge pumping. At 1.0 V, the access time is 25 ns and the current is 15 mA.

RF AMP IC for Optical Disc Player

This paper describes RF amp integrated circuit for the read channel of optical disc players that include CD and DVD demanding the equalizer and the decision block. A RF equalizer is composed of boosting filter to slim the data pulse and 9th order Bessel filter to attenuate high frequency noise. Boosting filter emphasize 6dB at 6MHz and maintains the linear phase within 1% by pole zero cancellation method. An important advantage is tuneability of the boosting and frequency characteristics by controlling the transconductance, therefore, it is enough to cover the tolerance of fabrication. The high frequency noise due to equalization is attenuated by 9th order Bessel filter which has the slope of over -42dB/oct. Measured jitter keeps within 4.5n. The decision block includes one bit analog to digital converter and the low pass filters to detect asymmetry and asymmetric amp. As the analog and the digital signals are mixed on a chip, the main ground and the NMOS bulk ground, DGND and AGND respectively, are separated. Also, it is laid out very carefully to minimize the digital noise in analog block Implemented in a 0.8um CMOS n-well technology, the RF equalizer and the decision block chip occupy 3000um × 1000um. Power consumption from asingle 5V is around 300mW.