Kuo-Fu Lee

3D device simulation of work function and interface trap fluctuations on high-κ / metal gate devices

This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-κ / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (σVth) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized σID > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gates WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.

Dynamic Characteristic Optimization of 14 a-Si:H TFTs Gate Driver Circuit Using Evolutionary Methodology for Display Panel Manufacturing

For thin-film transistor liquid crystal display (TFT-LCD) panel manufacturing, a gate driver circuit with amorphous silicon TFT plays an important role. In this paper, an amorphous silicon gate (ASG) driver circuit is optimized to improve circuits dynamic characteristics. The adopted simulation-based evolutionary method integrates genetic algorithm and circuit simulator on the unified optimization framework. The circuit consisting of 14 hydrogenated amorphous silicon TFTs (a-Si:H TFTs) used in a large panel is optimized for the given specifications of the rise time <; 1.5 μs, the fall time <; 1.5 μs, and the ripple voltage <;3 V with minimizing the total layout area. By optimizing the width and passive components of the 14 devices, the results of this study successfully meet the desired specifications, where the sensitivity analysis is further conducted to verify the characteristic variation with respect to the optimized parameters. To validate the results, the optimized circuit is fabricated with 4- μm a-Si:H TFT process, and the experimental result confirms the practicability of achieved design. The ripple voltage within 2.0 V is successfully obtained while the rise and fall times satisfy the required specifications for the fabricated sample. A 35% reduction of the optimized total devices width of a-Si:H TFTs is achieved.

Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants

Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.

Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits

This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high- frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal--Oxide--Semiconductor Field-Effect-Transistor Devices

In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal–oxide–semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation.

Gate driver circuit design optimization for TFT-LCD panel manufacturing

For TFT-LCD panel manufacturing, gate driver circuit with amorphous silicon thin-film transistor (TFT-ASG circuit) plays an important role. In this paper, we propose two different ASG driver circuit topologies to improve crucial dynamic characteristics and then optimize them with circuit sizing by simulation-based evolutionary method which integrates genetic algorithm and circuit simulator on the unified optimization framework [1]. The first circuit consisting of fourteen a-Si:H TFT devices is designed for the specifications of the rise time < 1.5 μs, the fall time < 1.5 μs and the ripple voltage < 3 V with the minimization of total layout area. The second one with eight a-Si:H TFTs and two capacitors is optimized with the additional constraint that power dissipation < 2 mW. The optimized results of this study successfully meet the desired specifications and sensitivity analysis of these results shows promising characteristics which could be used for optimal manufacturing of TFT-LCD panel.

Suppression of random-dopant-induced characteristic fluctuation in 16 nm MOSFET devices using dual-material gate

In this work, we for the first time explore the dual material gate (DMG) and inverse DMG devices for suppressing random dopant fluctuation (RDF)-induced characteristics fluctuation in 16-nm MOSFET devices. The physical mechanism of DMG devices to suppress RDF are investigated and discussed. The improvement of DMG for suppressing the RDF-induced Vth, Ion, and Ioff fluctuation are 28%, 12.3%, and 59%, respectively.

Electrical characteristic fluctuation and suppression in emerging CMOS device and circuit

We study the characteristic variability in high-к metal-gate CMOS device and circuit induced by various intrinsic fluctuation sources. Using an experimentally calibrated 3D device-and-circuit coupled simulation; we estimate the effect of metal-gate work-function fluctuation, oxide-thickness fluctuation, process-variation effect, and random-dopant fluctuation on device DC/AC characteristics. We then predict their impacts on transfer and dynamic properties of digital and analog circuits. Finally, variability suppression techniques are demonstrated from device engineering viewpoints.

Amorphous silicon thin-film transistor gate driver circuit design optimization using a simulation-based evolutionary technique

In this work, we for the first time optimize dynamic characteristic of amorphous silicon thin-film transistor (TFT) gate (ASG) driver circuits for TFT-LCD panel. The rise time, fall time, power dissipation, and ripple voltage of the ASG driver circuit are optimized using simulation-based evolutionary method which integrates genetic algorithm and circuit simulation on the unified optimization framework [1]. Two different a-Si:H TFT ASG driver circuits are optimized, the first circuit consisting of 14 a-Si:H TFT devices is designed for the specification of the rise time < 1.5 µs, the fall time < 1.5 µs and the ripple voltage < 3 V with the minimization of total layout area. The second one with 8 a-Si:H TFTs is further optimized with the power dissipation < 2 mW. The results of this study successfully met the desired specification; consequently, it benefits manufacturing of TFT-LCD panel.

Random-dopant-induced DC characteristic fluctuations in 16-nm-Gate LAC and inLAC MOSFET devices

Channel engineering is an effective way to suppress the random-dopant-induced characteristic fluctuation in nanometer-scale MOSFET devices. In this work, we study the effect of random dopants on characteristic fluctuations in 16-nm-gate lateral asymmetric channel (LAC) MOSFET devices. Devices with high channel doping concentration near the drain-end (the so-called inverse LAC; inLAC) can effectively improve DC characteristics fluctuation induced by random dopants. We have observed that the DC characteristic of the proposed inLAC MOSFET is less sensitive to random dopant, compared with conventional planar and LAC devices. Consequently, the inLAC MOSFET is further optimized for the best DC characteristic fluctuation reductions.