Chun-Yi Kuo

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware automatic test pattern generation. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by 22% and 10% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDFs are <; 5%.

A period tracking based on-chip sinusoidal jitter extraction technique

In this paper, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signals cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations

3D IC test scheduling using simulated annealing

Three-dimensional integrated circuits (3D ICs) have many advantages over traditional integrated circuits. Although 3D ICs have such advantages, there are many difficulties to be overcome. Testing for 3D ICs is regarded as the most difficult challenge. High power density in 3D ICs causes rising temperature, which may cause test yield loss. In this paper, we propose a thermal-aware test scheduling technique for 3D ICs. Our experimental results show that the maximum temperature in the test schedule of our proposed technique is under the temperature limit while the test length overhead is only 19%.

Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.

Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques

This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a pre-process to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique

To measure the variation of device Vt requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based on only the combined Id measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vt mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Id measurement per DUT.

Divide and conquer diagnosis for multiple defects

This paper presents a novel diagnosis technique for multiple defects. This technique proposes a simple heuristic to partition the failures log so that hard-to-detect defects and easy-to-detect defects are likely to be separated. This technique requires only commercial diagnosis software with a simple add-on tool. No customized diagnosis software is needed. Simulations on benchmark circuits demonstrated the effectiveness of the proposed technique. Real silicon experiments on a real industrial product have been verified by physical failure analysis that our technique does not lead to wrong diagnosis for single defect cases.