Jih-Nung Lee
Realtek
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Publication
Featured researches published by Jih-Nung Lee.
vlsi test symposium | 2017
Yu-Hao Huang; Ching-Ho Lu; Tse-Wei Wu; Yu-Teng Nien; Ying-Yen Chen; Max Wu; Jih-Nung Lee; Mango Chia-Tso Chao
This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.
asia and south pacific design automation conference | 2017
Tzu-Hsuan Huang; Wei-Tse Hung; Hao-Yu Yang; Wen-Hsiang Chang; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Mango Chia-Tso Chao
This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a pre-process to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.
vlsi test symposium | 2016
Chih-Ying Tsai; Kao-Chi Lee; Chien-Hsueh Lin; Sung-Chu Yu; Wen-Rong Liau; Alex Hou; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Mango Chia-Tso Chao
To measure the variation of device Vt requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based on only the combined Id measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vt mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Id measurement per DUT.
Archive | 2013
Ying-Yen Chen; Chen-Tung Lin; Jih-Nung Lee
Archive | 2012
Ying-Yen Chen; Jih-Nung Lee; Chun-Yu Yang
Archive | 2015
Yu-Cheng Lo; Ying-Yen Chen; Chao-Wen Tzeng; Jih-Nung Lee
Archive | 2012
Ying-Yen Chen; Jih-Nung Lee
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2018
Chien-Hsueh Lin; Chih-Ying Tsai; Kao-Chi Lee; Sung-Chu Yu; Wen-Rong Liau; Alex Hou; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Mango Chia-Tso Chao
Archive | 2015
Chao-Wen Tzeng; Ying-Yen Chen; Jih-Nung Lee
Archive | 2014
Yu-Cheng Lo; Ying-Yen Chen; Chao-Wen Tzeng; Jih-Nung Lee