Gunok Jung

A 0.004-mm

A portable multiphase clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented low power clock generator tile occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz

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A portable multiphase clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented low power clock generator tile occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz

Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm CMOS process indicate that the worst-case DQ delay of the proposed flip-flop is reduced by up to 59% while the energy-delay product is improved by up to 80% compared to the conventional master-slave flip-flop. The silicon results show that the new flip-flops function properly down to 0.62 V.

A 0.004mm/sup 2/ Portable Multiphase Clock Generator Tile for 1.2GHz RISC Microprocessor

In wide fan-in dynamic domino gates, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes which introduces a significant power penalty. In this paper, we propose a pulse domino technique to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, the gate input and the output terminals. Dynamic multiplexers designed and simulated in 90-nm CMOS are used to demonstrate the energy effectiveness of the proposed design style.

Scan-controlled pulse flip-flops for mobile application processors

This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650 MHz to 1.25 GHz.

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates

This paper describes a clock skew variation compensating technique for maintaining the skew amount between local clock meshes which have relative skew between them due to PVT variations and unbalanced load distribution. A skew detector that senses skew amount between clock meshes and converts it to effective logic values with a digitally controlled delay set which corrects the clock skew of the meshes enables 72% reduction in skew variation, from 160 ps to 45.2 ps.

Fully digital clock frequency doubler

This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm 2 CortexA-8 core with 65 nm Samsung process.