Youngmin Shin

28nm high-K metal gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

This paper presents a heterogeneous configuration of two different target quad-core CPUs. To support both high-performance and high energy-efficiency depending on application requirements, two types of quad-core CPUs are implemented in one mobile application processor. The first type quad-core CPU is designed to give the highest performance at the cost of reasonable power consumption. The second type quad-core CPU is optimized with emphasis on energy efficiency than high performance. This paper addresses the design features for high-performance quad-core CPU and the design optimization issue for low-power quad-core CPU. The best performance shows 1.8X of performance at the lowest power. The lowest power is reduced to 1/5 of power at the highest performance. Our heterogeneous configuration of separate implementations can be a more efficient solution for different power and performance requirements of various mobile applications.

Impaired strategic decision making in schizophrenia

Adaptive decision making in dynamic social settings requires frequent re-evaluation of choice outcomes and revision of strategies. This requires an array of multiple cognitive abilities, such as working memory and response inhibition. Thus, the disruption of such abilities in schizophrenia can have significant implications for social dysfunctions in affected patients. In the present study, 20 schizophrenia patients and 20 control subjects completed two computerized binary decision-making tasks. In the first task, the participants played a competitive zero-sum game against a computer in which the predictable choice behavior was penalized and the optimal strategy was to choose the two targets stochastically. In the second task, the expected payoffs of the two targets were fixed and unaffected by the subjects choices, so the optimal strategy was to choose the target with the higher expected payoff exclusively. The schizophrenia patients earned significantly less money during the first task, even though their overall choice probabilities were not significantly different from the control subjects. This was mostly because patients were impaired in integrating the outcomes of their previous choices appropriately in order to maintain the optimal strategy. During the second task, the choices of patients and control subjects displayed more similar patterns. This study elucidated the specific components in strategic decision making that are impaired in schizophrenia. The deficit, which can be characterized as strategic stiffness, may have implications for the poor social adjustment in schizophrenia patients.

28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

The proliferation of high-performance mobile devices is growing exponentially around the world. The essential driving force behind these ubiquitous devices is the high-performance CPU. To satisfy ever growing consumer demand for higher performance, a high-speed and multicore CPU configuration is mandatory, while energy efficiency is equally important for longer battery life. Furthermore, in order to support the wide range of performance (compute-intensive tasks, as well as less intensive tasks) required by todays mobile devices, a heterogeneous dual-CPU configuration comprising a high-performance CPU and an energy-efficient CPU can be one of the most energy efficient solutions for accomplishing both high-intensity and low-intensity tasks.

A 32nm high-k metal gate application processor with GHz multi-core CPU

Samsungs next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor

The demands for high-performance smart mobile devices are growing exponentially every year. Like the PC market, 64b CPUs are needed to meet this demand. Furthermore, mobile GPU performance is becoming increasingly important as mobile game graphics requirements are pushing the limits of GPU capabilities. For an enhanced mobile game user experience, a multi-core GPU is required. CPU/GPU power efficiency for longer battery life has been a major interest to consumers for many years. In order to support higher performance and power efficiency, two 64b quad-core CPUs with different microarchitectures and a hexa-core GPU are implemented using Samsungs 20nm gate-last high-k/metal-gate (HKMG) process.

A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices

This article introduces a 32 nm application processor designed for the latest high-performance smart handheld devices and discusses its design targets and options. To meet unprecedented levels of performance and data throughput demands, this processor employs a 200 MHz-1.6 GHz quad-core CPU, a quad-core GPU, a 2-port interleaving DRAM controller, dedicated video/audio/image processors, a camera/ display controller, and a hierarchical bus. This processor does it in a given power budget and battery life, and also in a given thermal budget by combining 32 nm high-k metal gate process technology with system-level power management techniques and dynamic thermal management techniques.

Intelligent governor for low-power mobile application processors

This paper introduces the power management schemes that control DVFS (Dynamic Voltage and Frequency Scaling) and core shutdown considering the characteristics of an application for the commercial application processors. Most power management schemes used in commercial application processors only monitor the CPU utilization to adjust the CPU frequency. Since recent application processors adopt multi-core CPU, the power management scheme, such as Hotplug, is necessary to manage the power state of the cores. However, none of the schemes mentioned above looks into the application characteristics for the power management. In this paper, we show that considering application characteristics is more beneficial for power management of recent commercial application processors.

Scan-controlled pulse flip-flops for mobile application processors

Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm CMOS process indicate that the worst-case DQ delay of the proposed flip-flop is reduced by up to 59% while the energy-delay product is improved by up to 80% compared to the conventional master-slave flip-flop. The silicon results show that the new flip-flops function properly down to 0.62 V.

Session 26 overview: Processor-power management and clocking

The first paper in this session considers optimization of computing systems at multiple levels from silicon to data center. A second paper pertains to power delivery network reliability and presents a software approach to mitigating worst-case droop. The remaining three papers deal with improving the power of the clock network by making it reconfigurable, use of adiabatic techniques and through adaptive frequency throttling.

Single-ended D flip-flop with implicit scan mux for high performance mobile AP

A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional master-slave flip-flop without any writeability issue at low voltage. The simulated and the measured results were made using a 14nm FinFET process. The data-to-output latency of the proposed flip-flop decreased by 51% while the power delay product improved by 41% as compared with the master-slave flip-flop. A test chip was fabricated in SS, TT, FF, SF and FS process corners and tested at −25C and 100C with a 50mV voltage step from 0.45V to 1.00V. It indicates both the master-slave and the proposed flip-flops can work down to 0.50V whereas conventional pulse-based flip-flops have writeability problems at 0.60V. Two product-level CPU designs were also fabricated for performance comparison, leading to 8.5% speed improvement by applying the proposed high-speed flip-flop.