Chung-Hsun Lin

BSIM-CMG: A Compact Model for Multi-Gate Transistors

The scaling of conventional planar CMOS is expected to become increasingly difficult due to increasing gate leakage and subthreshold leakage.[1-2] Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime.[3-4] The strong electrostatic control over the channel originating from the use of multiple gates reduces the coupling between source and drain in the subthreshold region and it enables the Multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness. Numerous efforts are underway to enable large scale manufacturing of multi-gate FETs. At the same time, circuit designers are beginning to design and evaluate multi-gate FET circuits.

BSIM5 MOSFET Model

This paper summarizes BSIM5 MOSFET model for aggressively scaled CMOS technology which was released recently. Various new physical effects are timely addressed in the new physical core including more accurate physics that is easily extended to non-charge-sheet, completely continuous current and derivatives, and extendibility to non-traditional CMOS based devices including SOI and double-gate MOSFETs. The flexible architecture also enables the carry-over of BSFM4s accurate modeling of numerous device behaviors attributable to device physics or technologies.

A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs using SPP approach

A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs is developed in this paper using the SPP (surface potential plus) approach. The essential difference of the present theory compared with the previous lies in that the Poisson equation is solved in the term of the electron concentration rather than the term of the surface potential. This solution formulates the electrical field surface potential in inversion charge terms rather than the surface potential. Thus, a non-charge-sheet-based analytical solution of inversion charge is obtained directly, replacing the solution of transcendent equation groups of the surface potential. The obtained inversion charge relation then serves to develop a non-charge-sheet-based analytical theory for undoped symmetric double-gate MOSFETs from the Pao-Sah current formulation. The formulated model has an analytic form that does not need to solve for the transcendent equation as in the conventional surface potentials or Pao-Sah formulation. The validity of the model has also been demonstrated by extensive comparison with AMD double-gate MOSFET data.

Circuit performance of double-gate SOI CMOS

The paper presents the performance of double-gate MOSFETs (DG MOSFET) in the circuit design perspective is examined via simulation using device structures based on the ITRS specification. The propagation delay (t/sub pd/) and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C/sub int/) between two stages, assuming reasonable input time and output loading capacitance. The performance result showed superiority of SDG device (symmetric double-gate device) over ADG device (asymmetric double-gate device) in speed and energy efficiency. Performance evaluation indicates that SDG SOI CMOS is the promising device for next generation high performance CMOS technology.

Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS

It is shown for the first time that HfSiON gate dielectric thickness has a strong impact on the flicker (1/f) noise of devices with Lg < 1mum. We have developed a simple model for both gate length (Lg) and HfSiON thickness dependences of N-FET flicker noise, based on excess traps at the gate-edges. P-FET noise does not exhibit such strong dependences. Scaling of future analog devices with high-k gate stack may be limited by noise considerations

Compact modeling of FinFETs featuring independent-gate operation mode

This paper describes the concept of the dynamic V/sub TH/ control in the compact modeling of FinFET. The model is implemented into Berkeley SPICE3 and verified with multiple-dimensional device simulator.

VDD Scaling for FinFET Logic and Memory Circuits: the Impact of Process Variations and SRAM Stability

As CMOS technology is fast moving towards the scaling limit, the FinFET is considered as the most promising structure down to 22nm node (Frank et al., 1992; Huang et al., 1999). Both FinFET-based logic and SRAM have been demonstrated recently (Rainey et al., 2002; Nowak et al.,2002). However, with scaling of the device dimensions, process-induced variations cause an increasing spread in the distribution of circuit delay and power, and affecting the robustness of VLSI designs (Burnett et al., 1994). SRAM has become the focus of technology scaling since embedded SRAM is estimated to occupy nearly 90% of the chip area in the near future (2003). Due to the area-constrained limit, the device fluctuation in the SRAM cell is significant. In this paper, we explore the performance of FinFET technology in digital circuit applications at 90 nm technology node under various device parameter variations. Comprehensive comparison of FinFET vis-a-vis PD-SOI has been done for logic gates as well as memory structures that are most commonly used in commercial VLSI designs. We also compare the performance of these two technologies at ultra-low voltages for future low-power applications

A Compact Quantum-Mechanical Model for Double-Gate MOSFET

A bias-dependent QM correction for surface potential calculation is derived for DG MOSFETs. The QM-corrected surface potential agrees with the 2D simulation results well. This indicates that both Vth shift in the subthreshold and strong inversion regions and gate capacitance degradation in the strong inversion region due to QM are predicted simultaneously. The model can predict the complicated QM effect dependence on various device parameters, such as Nbody, Tsi, Tox, etc

The next generation BSIM for sub-100nm mixed-signal circuit simulation

This paper outlines the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate physics that is easily extended to non-charge-sheet, completely continuous current and derivatives, and extendibility to non-traditional CMOS based devices including SOI and double-gate MOSFETs.

Compact Modeling for New Transistor Structures

Using embedded SRAM as a path, FinFET may enter manufacturing at 32nm. FinFET provides several advantages over the planar MOSFET structure—smaller size, larger current, smaller leakage, and less variation in threshold voltage. A compact model of multi-gate transistors will facilitate their adoption. BSIM-MG is a surface-potential based compact model of multi-gate MOSFETs fabricated on either SOI or bulk substrates. The effects of body doping are modeled. It can also model a double-gate transistor with independently biased front and back gates and asymmetric front and back gate work-functions and dielectric thicknesses.