Xuemei Xi

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

Modeling Advanced FET Technology in a Compact Model

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFET

Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances

A linearly graded doping drift region structure, a novel lateral voltage-sustained layer used for improvement of reduced surface field (RESURF) LDMOS transistor performance has been evaluated theoretically, numerically and experimentally in this paper for the first time. Due to the coupling effect of the two-dimensional (2D) electrical field, it is found from the theory developed here that the linearly graded drift region-doped profile can provide a high breakdown voltage while maintaining a high doping dose in the total drift region for minimizing the on-resistance Ron. The characteristics of such an LDMOS have been demonstrated by the 2D semiconductor device simulator MEDICI and further verified by our experimental results. We have obtained a reduction of the on-resistance of 50% from 10.3 mΩ cm2 to 5 mΩ cm2 in the on-state, and an increase of the breakdown voltage by a factor of 2.5 from 90 V to 234 V in the off-state, compared to the values for conventional RESURF devices. The experimental results verify the performance improvement predicted by the simulation and theory.

Normalized mutual integral difference method to extract threshold voltage of MOSFETs

A novel normalized mutual integral difference (NMID) method is presented in this letter to extract the threshold voltage of MOSFETs. The basic principle of this method is to utilize the exponential-linear characteristics of MOSFETs current so as to obtain the normalized mutual integral difference extreme spectral characteristics. The proposed method is sensitive to channel length variation while being insensitive to parasitic resistance. The extracted results on the threshold voltage show a good consistency and have been compared with those obtained by the second-derivative technique. A good correlation between both methods has also been found.

Circuit performance of double-gate SOI CMOS

The paper presents the performance of double-gate MOSFETs (DG MOSFET) in the circuit design perspective is examined via simulation using device structures based on the ITRS specification. The propagation delay (t/sub pd/) and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C/sub int/) between two stages, assuming reasonable input time and output loading capacitance. The performance result showed superiority of SDG device (symmetric double-gate device) over ADG device (asymmetric double-gate device) in speed and energy efficiency. Performance evaluation indicates that SDG SOI CMOS is the promising device for next generation high performance CMOS technology.

Compact modeling of FinFETs featuring independent-gate operation mode

This paper describes the concept of the dynamic V/sub TH/ control in the compact modeling of FinFET. The model is implemented into Berkeley SPICE3 and verified with multiple-dimensional device simulator.

Next generation CMOS compact models for RF and microwave applications

Commercial CMOS chips routinely operate at frequencies up to 5 GHz and exciting new opportunities exists in higher frequency bands such as 3-10 GHz, 17 GHz, 24 GHz, and 60 GHz. The Berkeley Wireless Research Center has demonstrated that standard 130 nm CMOS technology is capable of operation up to 60 GHz, enabling a host of new mm-wave applications such as Gb/s WLAN and compact radar imaging. Will circuit design and compact modeling continue along the same course, or is a new microwave design methodology required? This paper highlights the design and modeling challenges in moving up to these higher frequencies. A merger of RF and microwave design perspectives is used to offer insight into the problem. The paper discusses requirements for a next generation compact model to meet these challenges and offers potential solutions.

RETRACTED: Normalized mutual integral difference operator: a novel experimental method for extracting threshold voltage of MOSFETs

Normalized mutual integral difference operator (NMIDO), a novel experimental method for extracting the threshold voltage of MOSFETs, is presented in this paper. The basic principle of this method is to use the extreme spectrum characteristics of the NMIDO to find the threshold voltage. We have demonstrated numerically that this method is applied in the extraction of the threshold voltage of MOSFETs with different effective channel length and different parasitic series resistance cases. It has been shown that this method is sensitive to the channel length variation while insensitive to the parasitic resistance component. The extracted results on the threshold voltage of MOSFETs have also been compared with those obtained by the second-derivative method and the good agreement has been found, showing the advantage of the method presented here.

Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions

In this brief, an equivalent junction method is proposed to study three-dimensional (3-D) effect of the lateral curvature on curved-abrupt junctions. Analytical expressions including 3-D effect are derived to calculate the breakdown voltage, peak electrical field, and maximum depletion layer width of curved-abrupt junctions. The breakdown voltages calculated from the new analytic expression have been verified by the numerical simulation and experimental data. The equivalent junction model provides a simple means for device engineers to estimate the required substrate doping concentration, lateral curvature, junction depth and depletion width of a planar p-n junction with a specific breakdown voltage.

The impact of scaling on volume inversion in symmetric double-gate MOSFETs

In this paper, 2D and 3D DG structure are simulated by an ISE device simulator. As device scale down, volume inversion is a strong function of substrate doping and channel length. Therefore, an accurate and elaborate volume inversion model is essential for DG compact modeling.