Hao-Chieh Chang

Performance analysis and architecture evaluation of MPEG-4 video codec system

This paper presents various analyses of computational behavior. Namely, the number of datapath operations and memory access on the core profile level 2 (CPL2) of MPEG-4 video standard. These analyzed data exploit the load distribution and mode selection of the video system. The exploration of data-flow behavior and its derived computation of MPEG-4 video processing algorithms will then drive through an efficient architecture design.

A VLSI architecture design of VLC encoder for high data rate video/image coding

An efficient architecture of variable length coding (VLC) is developed for recent multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.

Scalable module-based architecture for MPEG-4 BMA motion estimation

In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module comprises one set of processing elements based on one-dimensional systolic array architecture. To support various applications, modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality.

A novel image compression algorithm by using Log-Exp transform

Based on the logarithmic and exponential transform, an efficient Log-Exp still image compression system is proposed. The Log-Exp compression is designed for the high quality still image, especially for the PSNR above 36. At similar image quality (Log-Exp PSNR=41.52 and JPEG PSNR=41.23), the Log-Exp compression can get a higher compression ratio than JPEG by a factor of1.84 times for the benchmark image Lena. Besides, the Log-Exp compression is computed in pixel-by-pixel without the block artifacts. In comparison with the JPEG compression result (bpp=0.99. PSNR=26.9), the Log-Exp compression uses less bpp (bpp=0.87) to get higher image quality (PSNR=36.38) for the benchmark image baboon.

VLSI architecture design of MPEG-4 shape coding

This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 video standard. The real-time constraint of MPEG-4 shape coding leads to a heavy computational bottleneck on todays computer architectures. To overcome this problem, design analysis and optimization of MPEG-4 shape coding are addressed. By utilizing the RISC-based model, computational behaviors of the MPEG-4 shape coding tool are carefully examined and analyzed. The characteristic of a large amount of bit-level data processing and data transfer of MPEG-4 shape coding motivates the optimization of bit-level data operations. Applying data-flow optimization and data reuse techniques, bit-level computation-efficient architectures, such as data-dispatch-based binary-shaped motion estimation, the delay-line model, and configurable context-based arithmetic coding, are designed to accelerate bit-level processing. These hardware blocks are integrated and scheduled in a very efficient data flow to achieve real-time performance for MPEG-4 CPL2 (core profile level 2) specification at 23.5 MHz clock rate. The system architecture is implemented using Verilog HDL and synthesized with a 0.35 /spl mu/m four-layer CMOS standard library.

Efficient algorithms and architectures for MPEG-4 object-based video coding

This paper presents efficient algorithms and architectures for the MPEG-4 object-based video coding. The novel coding tools supporting for object-based coding will much increase the computational burden, in comparison with conventional frame-based video coding system. In order to process these extra computational tasks effectively design techniques both on algorithms and architectures have to be addressed. By the careful examination of computational behavior of algorithms, the best-matched computation models can be derived, and the target architectures can be determined. Based on this design strategy, the computational behavior of the MPEG-4 video coding tools at simple/core profiles and level 2 is explored first. Then, by considering the analysis results, efficient algorithms and architectures are developed to meet the design specifications. The shape coding tool, which is the most computation-extensive task supporting for object-based functionality is selected as our study case. The real-time performance of shape coding can be easily achieved by the proposed architecture approximately running at 7.8 MHz while the optimized software running on a full-speed RISC (Ultra Sparc, 300 MHz) can only have about 1/10 performance.

Low power full-search block-matching motion estimation chip for H.263+

In this paper, a low power full-search block matching (FSBM) motion estimation design for the H.263+ low bit rate video coding was proposed. The features of H.263+ such as half-pixel precision and some advanced modes (advance prediction mode, PB-frame mode and reduced resolution update mode) are taken into consideration. This architecture can deal with different block size and searching range in a single chip without any latency. We use a 1-D and 2-D mixed architecture to fulfill this goal. To achieve the purpose of low power and reduce the design period, we use dual supply voltage levels in this chip. This chip is realized by TSMC 0.6 /spl mu/m single-poly triple-metal CMOS technology. The operation frequency is set at 60 MHz to meet the requirement of the real time processing in the reduced resolution update mode in H.263+. The power consumption is 424 mW at 60 MHz and the throughput is 36 frames per second with CIF format at 60 MHz.

Design and implementation of JPEG encoder IP core

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time re-configurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-um single-poly, triple-metal process. It can run up to 40 MHz at 3.3V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.

A Low Power 8 x 8 Direct 2-D DCT Chip Design

This paper presents the design and implementation of a low power 8 × 8 2-D DCT chip based on a computation-effective algorithm. Computational complexity can be reduced by simplifying the direct 2-D algorithm. Thus, the low power consumption is achieved due to complexity reduction. Besides, the parallel distributed-arithmetic (DA) technique is used to realize constant multiplication due to the low-power consideration. Additionally, the 2 V-power supply is practiced in circuit implementation for now and future battery operated applications. By using the TSMC 0.6 μm single-poly double-metal technology, 133 mW power consumption at 100 MHz and the 133 MHz maximum operation speed are achieved by critical path simulation.

Low power 2D DCT chip design for wireless multimedia terminals

In this paper, a low power 2-D DCT architecture based on direct 2-D approach is proposed. The direct 2-D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2-D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.