Hee-soon Chae

Retention Reliability of FinFET SONOS Device

This paper presents the retention reliability of the FinFET SONOS flash memory. By understanding the charge loss mechanisms of the SONOS structure, a new approach for the prediction of long term retention lifetime have been proposed. The comparison between the thermal-accelerated and field-accelerated lifetime has been demonstrated

Retention Mechanism of Localized Silicon–Oxide–Nitride–Oxide–Silicon Embedded NOR Device

Reliability studies of localized oxide–nitride–oxide memory (LONOM) devices are presented. The observed reduction in channel threshold voltage as a result of the retention charge loss of a programmed cell is demonstrated in terms of vertical leakage paths. Despite the apparent controversy of charge transport with nitride read-only memory (NROM) devices, the vertical paths are evidently observed via the channel and junction threshold voltage changes, which were monitored using Ids–Vds curves and gate-induced drain leakage (GIDL) measurements, visualizing the internal status of interface charges and stored charges in a nitride layer.

TWIn SONOS TransistOR (TWISTOR) for 2-bit/cell SONOS Memory Technology

In terms of nonvolatile memory device characteristics, the optimal device parameters for the TWISTOR (twin SONOS transistor) structure are investigated. Through this study, we show the best performance of 80nm gate TWISTOR device, which are very promising solution of future 2-bit/cell SONOS technology