Soo-doo Chae

Aligned carbon nanotubes for nanoelectronics

We discuss the central issues to be addressed for realizing carbon nanotube (CNT) nanoelectronics. We focus on selective growth, electron energy bandgap engineering and device integration. We have introduced a nanotemplate to control the selective growth, length and diameter of CNTs. Vertically aligned CNTs are synthesized for developing a vertical CNT-field effect transistor (FET). The ohmic contact of the CNT/metal interface is formed by rapid thermal annealing. Diameter control, synthesis of Y-shaped CNTs and surface modification of CNTs open up the possibility for energy bandgap modulation. The concepts of an ultra-high density transistor based on the vertical-CNT array and a nonvolatile memory based on the top gate structure with an oxide–nitride–oxide charge trap are also presented. We suggest that the deposited memory film can be used for the quantum dot storage due to the localized electric field created by a nano scale CNT-electron channel.

Carbon-nanotube-based nonvolatile memory with oxide–nitride–oxide film and nanoscale channel

We have fabricated a single-wall carbon-nanotube (CNT)-based nonvolatile memory device using SiO2–Si3N4–SiO2 (ONO) layers as a storage node. The memory device is composed of a top gate structure with a channel width of a few nanometers and the ONO layer embedded between CNT and gate electrode. When the bias voltage between the CNT and gate electrode increases to 4 V, charges are tunneled out from CNT surfaces and captured to the traps in the ONO layers. Stored charges on the trap sites make the threshold voltage shift of 60 mV and is independent of charging time, suggesting that the ONO has traps with a quasiquantized energy state. The quantized state is related to the localized high electric field associated with CNT channel. The CNT-field-effect transistor with an ONO storage node could be used for an ultrahigh-density nonvolatile memory.We have fabricated a single-wall carbon-nanotube (CNT)-based nonvolatile memory device using SiO2–Si3N4–SiO2 (ONO) layers as a storage node. The memory device is composed of a top gate structure with a channel width of a few nanometers and the ONO layer embedded between CNT and gate electrode. When the bias voltage between the CNT and gate electrode increases to 4 V, charges are tunneled out from CNT surfaces and captured to the traps in the ONO layers. Stored charges on the trap sites make the threshold voltage shift of 60 mV and is independent of charging time, suggesting that the ONO has traps with a quasiquantized energy state. The quantized state is related to the localized high electric field associated with CNT channel. The CNT-field-effect transistor with an ONO storage node could be used for an ultrahigh-density nonvolatile memory.

Fabrication and characterization of pre-aligned gallium nitride nanowire field-effect transistors

We report on the fabrication of gallium nitride (GaN) nanowire field-effect transistors (FETs) with both bottom-gate and top-gate structures, with very high yield using a unique pre-alignment process. The catalyst positions were chosen to be aligned with the source/drain position, and Ni catalysts with a diameter of 200 nm were deposited selectively at these pre-determined positions. Electrostatic analysis was performed for the bottom-gate devices to estimate the nanowires electrical characteristics. Comparison of the bottom-gate and the top-gate structures indicated that better performance, in terms of saturation and breakdown characteristics, can be obtained using the top-gate structure. For the top-gate nanowire FETs, temperature-dependent characteristics were investigated up to the current saturation regime, and memory effects were observed at room temperature.

Al-based Ohmic reflectors with low leakage currents and high reflectance for p-GaN flip-chip processes

The authors report the improvement of InGaN∕GaN light-emitting diodes on Al reflectors, commonly used as n-type GaN contacts. A Cu-doped indium oxide (CIO) (5nm)/indium tin oxide (ITO) (380nm) interlayer was deposited and annealed at 500°C, after which an Al (400nm)∕Ti–W (30nm) layer was sputtered on the ITO interlayer to reflect the light. The reflectance of CIO∕ITO∕Al∕Ti–W was ∼92% at 460nm, higher than that of the popular Ni∕Ag∕Pt scheme, and the forward voltage was 3.2–3.3V, similar to that of the Ni∕Ag∕Pt contact. Furthermore, the mean leakage current of CIO∕ITO∕Al∕Ti–W was 0.12μA, much lower than 0.54μA of Ni∕Ag∕Pt at −5V.

70 nm Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices Using Fowler-Nordheim Programming and Hot Hole Erase Method

70 nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with an ultra-thin oxide-nitride-oxide (ONO) film on an silicon-on-insulator (SOI) wafer are fabricated. If we consider the program/erase threshold voltage window as 2 V, the program time is approximately 1 ms at an 8 V program voltage and the erase time is about 200 us at a -6 V erase voltage using FN write and the 2-sided hot hole injection method. It is observed that the 2-sided hot hole injection can completely erase the electrons in the ONO thin film on a 70 nm channel. The memory window is almost constant after 100,000 cycles, and the retention characteristics show that the threshold voltage after 106 s is predicted as 0.75 V by extrapolation.

Improvement of electrical and optical properties of p-GaN Ohmic metals under ultraviolet light irradiation annealing processes

We report the improvement of electrical and optical properties of p-GaN Ohmic metals, ZnNi(10nm)∕Au(10nm), by ultraviolet (UV) light irradiation. After UV light irradiation, the specific contact resistance of p-GaN decreased slightly from 2.99×10−4to2.54×10−4Ωcm2, while the transmittance of the contact layer increased form 75% to 85% at a wavelength of 460nm. In addition, the forward voltage of InGaN∕GaN light-emitting diode chip at 20mA decreased from 3.55to3.45V, and the output power increased form 18to25mW by UV light irradiation. The low resistance and high transmittance of the p-GaN Ohmic metals are attributed to the reduced Shottky barrier by the formation of gallium oxide and the increased oxidation of p-Ohmic metals, respectively, due to ozone generated form oxygen during UV light irradiation.

A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatile Memories

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) [1] and nano-crystal memory [2] have been considered as a replacement floating gate memory due to simple process, low voltage operation and high speed. In the SONOS memory, an ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention. This may allow longer retention with thinner tunneling dielectrics, leading to lower operating voltages. However for the high speed performance, SONOS needs improvement in erase time the discharging process of electrons from the traps. Thus we have speculated on the effect of electric fields in the trapping-control gate region, and characterized the effects of doping on poly-silicon gate in SONOS memory device. Our experiments compare the characteristics of SONOS memories between n+ type and p+ type polysilicon gate. Figure 1 shows the schematics of these structures. SONOS memory devices have been fabricated with 0.5 um n+ type gate or p+ type gate on SOI substrates using the conventional CMOS processing technology. The tunneling oxide of 3 nm thickness was grown at 900 C and then a Si3N4 film of 5.5 nm and the blocking oxide layer of 7 nm were deposited by low pressure chemical vapor deposition (LPCVD). Figure 2 shows a transmission-electron micrograph of the cross-section of this grown and deposited memory stack with the dark region as the silicon nitride. After these gate stacks process, n+ type or p+ type poly-silicon is deposited. Using the program/erase threshold voltage window as 4 V in p+ type poly-silicon gate memory, the program time is approximately 20 us at 16 V program voltage and the erase time is about 1 ms at a –16 V erase voltage using FN tunneling method. The capture and erase characteristics also show asymmetries in the capture and erase processes due to the physical differences in the processes themselves. The capture process is based on Fowler-Nordheim injection where the relevant capture cross-section is related to the extent of the potential perturbation of the defect. This capture crosssection is one to two orders of magnitude smaller than that of silicon nanocrystals. The erasure process is presumably a Poole-Frenkel mechanism, or other similar de-trapping process with strong localization and field-dependence. The erase time of SONOS memory device is somewhat slow, and it is due to the injection of electrons through top oxide from the gate and heavy mass of holes. To solve this problem, several methods have been introduced recently. Using a high k material instead of SiO2 thin film is useful for decreasing the transmission of electrons in the top oxide due to the capacitive coupling [3]. However, this may not be suitable technologically in a CMOS process. We expect that the higher work-function of p-type gate to improve erase speed. Figure 4 shows that the erase speed of p+ gate is much faster than that of n+ gate. The work will describe detailed experimental measurements in support of this conclusion.

The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices

In the use of single/few electrons in distributed storage for non-volatile, low power, and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has dependence and the devices operate with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of LDD process are investigated to draw these conclusions.